Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	157831480	0	0	0
ctrl_en_input_filter_rd_A	157831480	63620	0	0
intr_ctrl_en_falling_rd_A	157831480	64001	0	0
intr_ctrl_en_lvlhigh_rd_A	157831480	63412	0	0
intr_ctrl_en_lvllow_rd_A	157831480	63910	0	0
intr_ctrl_en_rising_rd_A	157831480	63347	0	0
intr_enable_rd_A	157831480	63169	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157831480	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157831480	63620	0	0
T1	930628	2033	0	0
T2	7932	7	0	0
T3	9825	4	0	0
T4	0	4	0	0
T5	0	2	0	0
T6	0	3	0	0
T7	0	295	0	0
T8	0	292	0	0
T9	0	3565	0	0
T10	0	164	0	0
T11	5788	0	0	0
T12	290465	0	0	0
T13	2411	0	0	0
T14	4644	0	0	0
T15	16688	0	0	0
T16	183018	0	0	0
T17	8224	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157831480	64001	0	0
T1	930628	2198	0	0
T2	7932	0	0	0
T3	9825	3	0	0
T4	0	2	0	0
T5	0	7	0	0
T6	0	16	0	0
T7	0	309	0	0
T8	0	339	0	0
T9	0	3510	0	0
T10	0	141	0	0
T11	5788	0	0	0
T12	290465	0	0	0
T13	2411	0	0	0
T14	4644	0	0	0
T15	16688	0	0	0
T16	183018	0	0	0
T17	8224	0	0	0
T18	0	8	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157831480	63412	0	0
T1	930628	2217	0	0
T2	7932	0	0	0
T6	0	17	0	0
T7	0	285	0	0
T8	0	333	0	0
T9	0	3501	0	0
T10	0	117	0	0
T11	5788	0	0	0
T12	290465	0	0	0
T13	2411	0	0	0
T18	0	5	0	0
T19	4517	3	0	0
T20	0	4725	0	0
T21	0	102	0	0
T22	3258	0	0	0
T23	4809	0	0	0
T24	2716	0	0	0
T25	1750	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157831480	63910	0	0
T1	930628	2119	0	0
T2	7932	5	0	0
T3	0	7	0	0
T6	0	4	0	0
T7	0	287	0	0
T8	0	319	0	0
T9	0	3759	0	0
T10	0	141	0	0
T11	5788	0	0	0
T12	290465	0	0	0
T13	2411	0	0	0
T18	0	1	0	0
T19	4517	2	0	0
T22	3258	0	0	0
T23	4809	0	0	0
T24	2716	0	0	0
T25	1750	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157831480	63347	0	0
T1	930628	2248	0	0
T2	7932	0	0	0
T3	0	3	0	0
T4	0	2	0	0
T5	0	2	0	0
T6	0	6	0	0
T7	0	275	0	0
T8	0	317	0	0
T9	0	3536	0	0
T10	0	114	0	0
T11	5788	0	0	0
T12	290465	0	0	0
T13	2411	0	0	0
T19	4517	1	0	0
T22	3258	0	0	0
T23	4809	0	0	0
T24	2716	0	0	0
T25	1750	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157831480	63169	0	0
T1	930628	2424	0	0
T2	7932	0	0	0
T3	9825	13	0	0
T5	0	5	0	0
T6	0	3	0	0
T7	0	361	0	0
T8	0	380	0	0
T9	0	3580	0	0
T10	0	73	0	0
T11	5788	0	0	0
T12	290465	0	0	0
T13	2411	0	0	0
T14	4644	0	0	0
T15	16688	0	0	0
T16	183018	0	0	0
T17	8224	0	0	0
T20	0	4644	0	0
T21	0	80	0	0