Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4036469	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17780270

1

T23

266

T1

2092

T11

691

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8761121	1			T23	197		T1	1328		T11	317
values[0x0]	6423538	1			T23	71		T1	725		T11	269
values[0x1]	6632080	1			T23	81		T1	714		T11	272

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3111417	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18705322

1

T23

281

T1

2227

T11

719

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	88399	1			T23	4		T1	8		T11	3
valid_sources[0x01]	88011	1			T1	9		T11	3		T15	9
valid_sources[0x02]	76089	1			T23	3		T1	14		T11	2
valid_sources[0x03]	80025	1			T23	3		T1	13		T11	1
valid_sources[0x04]	83609	1			T1	8		T11	2		T15	6
valid_sources[0x05]	131039	1			T23	1		T1	16		T11	2
valid_sources[0x06]	77141	1			T1	7		T11	3		T14	1
valid_sources[0x07]	91407	1			T1	9		T11	10		T16	1
valid_sources[0x08]	78756	1			T1	7		T11	1		T16	1
valid_sources[0x09]	77645	1			T1	13		T11	2		T15	1
valid_sources[0x0a]	83283	1			T23	3		T1	11		T11	3
valid_sources[0x0b]	77377	1			T1	15		T11	3		T17	1
valid_sources[0x0c]	84553	1			T23	4		T1	8		T11	7
valid_sources[0x0d]	78516	1			T1	17		T16	2		T17	2
valid_sources[0x0e]	74625	1			T23	8		T1	4		T14	1
valid_sources[0x0f]	78236	1			T1	16		T11	9		T17	1
valid_sources[0x10]	77801	1			T1	12		T11	6		T16	2
valid_sources[0x11]	81869	1			T1	15		T11	3		T16	1
valid_sources[0x12]	75530	1			T1	10		T17	3		T19	3
valid_sources[0x13]	83985	1			T1	10		T15	6		T17	1
valid_sources[0x14]	225637	1			T1	12		T11	5		T15	1
valid_sources[0x15]	86568	1			T23	1		T1	9		T11	3
valid_sources[0x16]	102519	1			T1	7		T11	6		T14	2
valid_sources[0x17]	92376	1			T1	9		T11	6		T15	1
valid_sources[0x18]	75764	1			T1	10		T11	1		T14	1
valid_sources[0x19]	80054	1			T23	4		T1	7		T11	6
valid_sources[0x1a]	90481	1			T1	13		T11	1		T17	1
valid_sources[0x1b]	79014	1			T1	8		T11	5		T14	3
valid_sources[0x1c]	80990	1			T23	2		T1	11		T11	1
valid_sources[0x1d]	149434	1			T1	15		T14	2		T15	14
valid_sources[0x1e]	76660	1			T1	19		T11	8		T14	1
valid_sources[0x1f]	81113	1			T1	9		T11	2		T112	2
valid_sources[0x20]	72658	1			T1	10		T11	2		T14	3
valid_sources[0x21]	83415	1			T1	10		T11	5		T16	1
valid_sources[0x22]	80383	1			T23	2		T1	5		T11	5
valid_sources[0x23]	77985	1			T1	10		T11	1		T15	2
valid_sources[0x24]	83970	1			T1	5		T11	1		T14	8
valid_sources[0x25]	85665	1			T1	6		T11	5		T15	6
valid_sources[0x26]	86950	1			T1	10		T11	6		T15	5
valid_sources[0x27]	82649	1			T23	4		T1	13		T11	7
valid_sources[0x28]	77840	1			T1	15		T11	3		T15	4
valid_sources[0x29]	81205	1			T1	9		T11	4		T16	4
valid_sources[0x2a]	73074	1			T1	15		T11	1		T16	4
valid_sources[0x2b]	83286	1			T1	6		T11	6		T15	2
valid_sources[0x2c]	83586	1			T23	2		T1	14		T11	2
valid_sources[0x2d]	84571	1			T23	2		T1	6		T15	1
valid_sources[0x2e]	77866	1			T1	17		T11	5		T17	1
valid_sources[0x2f]	74096	1			T1	10		T11	6		T16	1
valid_sources[0x30]	81287	1			T1	17		T11	2		T15	1
valid_sources[0x31]	82793	1			T1	11		T11	3		T15	1
valid_sources[0x32]	79415	1			T23	8		T1	18		T11	6
valid_sources[0x33]	82308	1			T1	11		T11	4		T15	4
valid_sources[0x34]	76782	1			T23	1		T1	8		T15	2
valid_sources[0x35]	77064	1			T1	11		T11	5		T14	1
valid_sources[0x36]	77301	1			T1	11		T11	5		T14	3
valid_sources[0x37]	75984	1			T23	9		T1	11		T11	5
valid_sources[0x38]	83474	1			T1	11		T11	1		T15	1
valid_sources[0x39]	85201	1			T1	16		T11	1		T16	3
valid_sources[0x3a]	78589	1			T1	5		T11	2		T15	8
valid_sources[0x3b]	81910	1			T1	11		T11	3		T112	2
valid_sources[0x3c]	82418	1			T1	9		T11	6		T15	3
valid_sources[0x3d]	74641	1			T1	10		T11	1		T15	1
valid_sources[0x3e]	78169	1			T23	2		T1	17		T11	7
valid_sources[0x3f]	78587	1			T1	18		T11	4		T15	2
valid_sources[0x40]	78316	1			T1	14		T11	4		T16	1
valid_sources[0x41]	77613	1			T1	11		T11	10		T15	1
valid_sources[0x42]	81403	1			T23	7		T1	19		T11	2
valid_sources[0x43]	82043	1			T1	7		T11	4		T16	2
valid_sources[0x44]	85017	1			T23	4		T1	8		T11	9
valid_sources[0x45]	92938	1			T1	19		T11	3		T16	3
valid_sources[0x46]	79800	1			T1	14		T11	4		T15	5
valid_sources[0x47]	82678	1			T1	15		T11	3		T15	1
valid_sources[0x48]	88776	1			T1	10		T11	1		T16	1
valid_sources[0x49]	74692	1			T1	15		T11	2		T15	1
valid_sources[0x4a]	87356	1			T23	9		T1	7		T11	1
valid_sources[0x4b]	76696	1			T1	11		T11	6		T15	5
valid_sources[0x4c]	79409	1			T1	9		T11	4		T15	3
valid_sources[0x4d]	91057	1			T23	1		T1	18		T14	7
valid_sources[0x4e]	77437	1			T1	19		T11	4		T14	1
valid_sources[0x4f]	82952	1			T1	14		T11	1		T16	1
valid_sources[0x50]	80615	1			T1	13		T11	6		T16	2
valid_sources[0x51]	77883	1			T1	8		T11	2		T15	4
valid_sources[0x52]	78860	1			T1	11		T11	6		T16	4
valid_sources[0x53]	83072	1			T1	6		T11	4		T15	1
valid_sources[0x54]	74126	1			T1	18		T11	2		T14	2
valid_sources[0x55]	87735	1			T23	10		T1	13		T11	5
valid_sources[0x56]	82767	1			T1	7		T11	1		T15	3
valid_sources[0x57]	77393	1			T1	8		T11	4		T17	1
valid_sources[0x58]	76056	1			T1	13		T11	7		T112	4
valid_sources[0x59]	75865	1			T23	3		T1	9		T11	5
valid_sources[0x5a]	84462	1			T1	9		T11	4		T16	1
valid_sources[0x5b]	86118	1			T1	11		T11	3		T15	9
valid_sources[0x5c]	79073	1			T23	3		T1	12		T11	2
valid_sources[0x5d]	79354	1			T1	11		T11	3		T16	1
valid_sources[0x5e]	89929	1			T1	14		T11	1		T16	2
valid_sources[0x5f]	84531	1			T1	12		T11	1		T17	1
valid_sources[0x60]	79009	1			T23	25		T1	8		T11	3
valid_sources[0x61]	82297	1			T1	9		T11	1		T17	2
valid_sources[0x62]	86154	1			T1	11		T15	3		T16	1
valid_sources[0x63]	81945	1			T23	2		T1	8		T11	3
valid_sources[0x64]	81410	1			T1	11		T11	1		T15	3
valid_sources[0x65]	80097	1			T23	2		T1	6		T11	6
valid_sources[0x66]	80615	1			T1	10		T11	2		T15	1
valid_sources[0x67]	80412	1			T1	10		T11	1		T17	1
valid_sources[0x68]	74654	1			T23	6		T1	8		T11	4
valid_sources[0x69]	80954	1			T1	9		T11	3		T15	3
valid_sources[0x6a]	80835	1			T1	11		T11	2		T16	2
valid_sources[0x6b]	78566	1			T1	9		T16	7		T17	2
valid_sources[0x6c]	76597	1			T1	11		T11	5		T17	1
valid_sources[0x6d]	87518	1			T1	12		T11	2		T15	4
valid_sources[0x6e]	89431	1			T1	7		T11	3		T15	4
valid_sources[0x6f]	116006	1			T23	3		T1	9		T15	2
valid_sources[0x70]	83405	1			T1	11		T11	3		T14	1
valid_sources[0x71]	84014	1			T1	8		T11	2		T17	2
valid_sources[0x72]	84452	1			T1	14		T11	4		T14	4
valid_sources[0x73]	81272	1			T23	3		T1	9		T11	1
valid_sources[0x74]	82026	1			T1	9		T11	4		T15	1
valid_sources[0x75]	79986	1			T23	2		T1	10		T11	4
valid_sources[0x76]	92222	1			T1	15		T11	3		T16	4
valid_sources[0x77]	79268	1			T1	16		T11	5		T16	2
valid_sources[0x78]	82140	1			T1	4		T11	2		T15	3
valid_sources[0x79]	81398	1			T1	11		T11	10		T15	3
valid_sources[0x7a]	91294	1			T1	7		T11	1		T15	2
valid_sources[0x7b]	87298	1			T1	9		T11	3		T14	8
valid_sources[0x7c]	81023	1			T1	14		T11	3		T17	1
valid_sources[0x7d]	72618	1			T23	4		T1	16		T11	2
valid_sources[0x7e]	83713	1			T1	11		T11	1		T16	2
valid_sources[0x7f]	135976	1			T1	16		T11	3		T14	5
valid_sources[0x80]	83983	1			T23	3		T1	12		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4979237

1

T23

114

T1

653

T11

150

values[0x0]

all_enables

biggest_size

6401963

1

T23

71

T1

725

T11

269

values[0x1]

all_enables

biggest_size

6399070

1

T23

81

T1

714

T11

272