Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	165275736	0	0	0
ctrl_en_input_filter_rd_A	165275736	43089	0	0
intr_ctrl_en_falling_rd_A	165275736	43177	0	0
intr_ctrl_en_lvlhigh_rd_A	165275736	42506	0	0
intr_ctrl_en_lvllow_rd_A	165275736	42790	0	0
intr_ctrl_en_rising_rd_A	165275736	43003	0	0
intr_enable_rd_A	165275736	42346	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165275736	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165275736	43089	0	0
T1	31032	214	0	0
T2	0	2106	0	0
T3	0	122	0	0
T4	0	11	0	0
T5	0	140	0	0
T6	0	176	0	0
T7	0	625	0	0
T8	0	3	0	0
T9	0	231	0	0
T10	0	101	0	0
T11	13459	0	0	0
T12	2808	0	0	0
T13	3676	0	0	0
T14	3643	0	0	0
T15	6085	0	0	0
T16	5543	0	0	0
T17	2859	0	0	0
T18	7786	0	0	0
T19	4624	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165275736	43177	0	0
T1	31032	180	0	0
T2	0	2089	0	0
T3	0	145	0	0
T4	0	9	0	0
T5	0	130	0	0
T6	0	163	0	0
T7	0	703	0	0
T8	0	5	0	0
T9	0	273	0	0
T10	0	130	0	0
T11	13459	0	0	0
T12	2808	0	0	0
T13	3676	0	0	0
T14	3643	0	0	0
T15	6085	0	0	0
T16	5543	0	0	0
T17	2859	0	0	0
T18	7786	0	0	0
T19	4624	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165275736	42506	0	0
T1	31032	212	0	0
T2	0	1897	0	0
T3	0	148	0	0
T5	0	131	0	0
T6	0	258	0	0
T7	0	709	0	0
T9	0	218	0	0
T10	0	109	0	0
T11	13459	0	0	0
T12	2808	0	0	0
T13	3676	0	0	0
T14	3643	0	0	0
T15	6085	0	0	0
T16	5543	0	0	0
T17	2859	0	0	0
T18	7786	0	0	0
T19	4624	0	0	0
T20	0	5	0	0
T21	0	3943	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165275736	42790	0	0
T1	31032	218	0	0
T2	0	2027	0	0
T3	0	135	0	0
T5	0	135	0	0
T6	0	166	0	0
T7	0	687	0	0
T9	0	339	0	0
T10	0	127	0	0
T11	13459	0	0	0
T12	2808	0	0	0
T13	3676	0	0	0
T14	3643	0	0	0
T15	6085	0	0	0
T16	5543	0	0	0
T17	2859	0	0	0
T18	7786	0	0	0
T19	4624	0	0	0
T21	0	4222	0	0
T22	0	604	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165275736	43003	0	0
T1	31032	248	0	0
T2	0	2032	0	0
T3	0	137	0	0
T5	0	94	0	0
T6	0	199	0	0
T7	0	696	0	0
T9	0	320	0	0
T10	0	99	0	0
T11	13459	0	0	0
T12	2808	0	0	0
T13	3676	0	0	0
T14	3643	0	0	0
T15	6085	0	0	0
T16	5543	0	0	0
T17	2859	0	0	0
T18	7786	0	0	0
T19	4624	0	0	0
T21	0	3931	0	0
T22	0	701	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165275736	42346	0	0
T1	31032	213	0	0
T2	0	2045	0	0
T3	0	102	0	0
T4	0	7	0	0
T5	0	115	0	0
T6	0	199	0	0
T7	0	672	0	0
T9	0	314	0	0
T10	0	123	0	0
T11	13459	0	0	0
T12	2808	0	0	0
T13	3676	0	0	0
T14	3643	0	0	0
T15	6085	0	0	0
T16	5543	0	0	0
T17	2859	0	0	0
T18	7786	0	0	0
T19	4624	0	0	0
T20	0	1	0	0