Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3665111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16720179

1

T23

240

T24

176

T25

150

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8063410	1			T23	38		T24	24		T25	93
values[0x0]	6047581	1			T23	118		T24	82		T25	46
values[0x1]	6274299	1			T23	98		T24	82		T25	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2808421	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17576869

1

T23

241

T24

178

T25

159

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	73080	1			T24	2		T1	13		T13	1
valid_sources[0x01]	84689	1			T24	1		T25	1		T1	13
valid_sources[0x02]	71750	1			T24	1		T1	31		T17	8
valid_sources[0x03]	72740	1			T1	8		T17	6		T18	780
valid_sources[0x04]	82186	1			T24	1		T25	1		T1	4
valid_sources[0x05]	81527	1			T24	2		T25	2		T1	9
valid_sources[0x06]	104919	1			T1	5		T12	10		T17	7
valid_sources[0x07]	77015	1			T24	1		T1	9		T12	3
valid_sources[0x08]	74597	1			T25	2		T1	15		T11	1
valid_sources[0x09]	80210	1			T25	1		T1	16		T17	15
valid_sources[0x0a]	79047	1			T24	3		T1	13		T17	11
valid_sources[0x0b]	78844	1			T24	3		T1	5		T17	11
valid_sources[0x0c]	79388	1			T25	1		T1	12		T12	4
valid_sources[0x0d]	78597	1			T25	1		T1	12		T12	5
valid_sources[0x0e]	69754	1			T25	1		T1	6		T17	11
valid_sources[0x0f]	78811	1			T25	1		T1	8		T17	9
valid_sources[0x10]	80565	1			T24	2		T25	1		T1	7
valid_sources[0x11]	77544	1			T1	22		T12	2		T17	12
valid_sources[0x12]	183014	1			T24	1		T1	7		T11	1
valid_sources[0x13]	78851	1			T1	19		T17	10		T18	758
valid_sources[0x14]	74912	1			T24	2		T1	16		T13	2
valid_sources[0x15]	74463	1			T25	1		T1	3		T12	2
valid_sources[0x16]	76648	1			T24	1		T25	4		T1	10
valid_sources[0x17]	74572	1			T24	1		T1	20		T12	12
valid_sources[0x18]	77057	1			T25	1		T1	7		T12	7
valid_sources[0x19]	82713	1			T1	18		T11	1		T12	3
valid_sources[0x1a]	72719	1			T24	1		T25	1		T1	15
valid_sources[0x1b]	77852	1			T25	2		T1	14		T12	2
valid_sources[0x1c]	72351	1			T24	3		T1	9		T12	11
valid_sources[0x1d]	71095	1			T25	3		T1	6		T17	3
valid_sources[0x1e]	71260	1			T25	1		T1	16		T17	9
valid_sources[0x1f]	76466	1			T24	1		T25	1		T1	9
valid_sources[0x20]	75978	1			T24	1		T1	5		T12	1
valid_sources[0x21]	71604	1			T24	2		T25	1		T1	11
valid_sources[0x22]	79346	1			T25	2		T1	13		T11	1
valid_sources[0x23]	78456	1			T24	4		T25	1		T1	7
valid_sources[0x24]	77834	1			T24	1		T25	1		T1	6
valid_sources[0x25]	76087	1			T1	19		T12	5		T17	4
valid_sources[0x26]	85130	1			T1	9		T12	4		T17	9
valid_sources[0x27]	70885	1			T24	3		T25	3		T1	8
valid_sources[0x28]	73191	1			T1	7		T12	7		T17	9
valid_sources[0x29]	72105	1			T24	1		T25	2		T1	10
valid_sources[0x2a]	81993	1			T1	10		T12	1		T17	6
valid_sources[0x2b]	76402	1			T24	3		T25	2		T1	9
valid_sources[0x2c]	76413	1			T1	14		T13	1		T17	10
valid_sources[0x2d]	72168	1			T24	1		T1	18		T11	1
valid_sources[0x2e]	73052	1			T1	10		T12	1		T17	12
valid_sources[0x2f]	74991	1			T24	1		T25	2		T1	6
valid_sources[0x30]	74319	1			T24	2		T25	2		T1	20
valid_sources[0x31]	79472	1			T1	12		T17	11		T18	768
valid_sources[0x32]	71053	1			T24	1		T1	19		T11	1
valid_sources[0x33]	77920	1			T1	9		T12	2		T13	1
valid_sources[0x34]	78179	1			T25	2		T1	9		T17	8
valid_sources[0x35]	74649	1			T25	1		T1	5		T17	9
valid_sources[0x36]	74900	1			T1	25		T12	3		T13	2
valid_sources[0x37]	83448	1			T25	1		T1	13		T12	3
valid_sources[0x38]	74671	1			T1	14		T17	6		T18	738
valid_sources[0x39]	71352	1			T1	26		T17	8		T18	768
valid_sources[0x3a]	77171	1			T24	2		T25	1		T1	9
valid_sources[0x3b]	78247	1			T24	3		T1	8		T17	14
valid_sources[0x3c]	73932	1			T24	2		T1	4		T12	9
valid_sources[0x3d]	74298	1			T25	3		T1	5		T13	1
valid_sources[0x3e]	70959	1			T25	1		T1	4		T12	2
valid_sources[0x3f]	72666	1			T1	7		T17	8		T18	720
valid_sources[0x40]	78872	1			T24	3		T1	7		T17	13
valid_sources[0x41]	76521	1			T24	1		T25	2		T1	11
valid_sources[0x42]	71672	1			T25	2		T1	14		T12	1
valid_sources[0x43]	74556	1			T1	8		T17	8		T18	734
valid_sources[0x44]	79323	1			T1	15		T17	10		T18	794
valid_sources[0x45]	81258	1			T1	16		T12	2		T17	11
valid_sources[0x46]	75654	1			T1	10		T12	1		T17	12
valid_sources[0x47]	84356	1			T1	14		T12	2		T17	8
valid_sources[0x48]	74942	1			T25	1		T1	16		T12	12
valid_sources[0x49]	77055	1			T24	1		T1	18		T12	1
valid_sources[0x4a]	74840	1			T1	5		T17	11		T18	831
valid_sources[0x4b]	197443	1			T25	1		T1	2		T17	9
valid_sources[0x4c]	72782	1			T1	12		T12	5		T17	6
valid_sources[0x4d]	76930	1			T24	2		T25	1		T1	8
valid_sources[0x4e]	84085	1			T25	1		T1	10		T12	4
valid_sources[0x4f]	75453	1			T24	4		T1	24		T17	10
valid_sources[0x50]	79560	1			T24	3		T25	1		T1	6
valid_sources[0x51]	73025	1			T25	1		T1	9		T12	7
valid_sources[0x52]	73419	1			T25	2		T1	9		T17	9
valid_sources[0x53]	78119	1			T24	3		T1	10		T12	1
valid_sources[0x54]	75156	1			T24	1		T25	1		T1	12
valid_sources[0x55]	76726	1			T25	1		T1	11		T17	9
valid_sources[0x56]	74587	1			T1	14		T11	1		T17	11
valid_sources[0x57]	83823	1			T1	20		T17	13		T18	778
valid_sources[0x58]	81480	1			T24	1		T1	6		T13	1
valid_sources[0x59]	75664	1			T1	8		T12	2		T17	8
valid_sources[0x5a]	77560	1			T25	1		T1	13		T11	1
valid_sources[0x5b]	74453	1			T25	1		T1	19		T12	1
valid_sources[0x5c]	72099	1			T24	2		T1	7		T12	4
valid_sources[0x5d]	74316	1			T25	1		T1	11		T12	7
valid_sources[0x5e]	77141	1			T24	1		T25	1		T1	9
valid_sources[0x5f]	79858	1			T25	1		T1	14		T12	6
valid_sources[0x60]	70378	1			T24	2		T1	8		T12	3
valid_sources[0x61]	76654	1			T24	1		T25	4		T1	9
valid_sources[0x62]	77197	1			T24	4		T1	7		T17	4
valid_sources[0x63]	75405	1			T24	2		T1	7		T11	1
valid_sources[0x64]	77061	1			T1	10		T12	15		T17	11
valid_sources[0x65]	74235	1			T25	2		T1	7		T12	2
valid_sources[0x66]	73765	1			T25	1		T1	4		T12	4
valid_sources[0x67]	77576	1			T25	2		T1	4		T17	8
valid_sources[0x68]	71738	1			T24	2		T1	17		T17	13
valid_sources[0x69]	73108	1			T1	17		T17	9		T18	723
valid_sources[0x6a]	73141	1			T25	1		T1	10		T17	10
valid_sources[0x6b]	193163	1			T25	1		T1	7		T12	5
valid_sources[0x6c]	71278	1			T25	1		T1	19		T17	12
valid_sources[0x6d]	79493	1			T24	1		T25	1		T1	10
valid_sources[0x6e]	72477	1			T24	1		T1	13		T12	4
valid_sources[0x6f]	78195	1			T1	6		T12	3		T17	12
valid_sources[0x70]	74734	1			T25	1		T1	20		T12	1
valid_sources[0x71]	72763	1			T25	2		T1	11		T17	7
valid_sources[0x72]	76617	1			T25	1		T1	8		T12	3
valid_sources[0x73]	82624	1			T1	17		T17	8		T18	749
valid_sources[0x74]	75243	1			T25	1		T1	9		T17	5
valid_sources[0x75]	72755	1			T24	2		T25	1		T1	10
valid_sources[0x76]	75256	1			T25	1		T1	5		T17	8
valid_sources[0x77]	71107	1			T24	1		T25	2		T1	3
valid_sources[0x78]	78688	1			T1	4		T12	3		T17	9
valid_sources[0x79]	75733	1			T24	2		T25	1		T1	4
valid_sources[0x7a]	81362	1			T25	1		T1	5		T17	8
valid_sources[0x7b]	73727	1			T1	3		T13	1		T17	5
valid_sources[0x7c]	105157	1			T24	5		T1	9		T17	2
valid_sources[0x7d]	71961	1			T25	1		T1	8		T12	1
valid_sources[0x7e]	75983	1			T25	1		T1	10		T12	9
valid_sources[0x7f]	77227	1			T24	2		T25	1		T1	5
valid_sources[0x80]	75443	1			T24	1		T1	15		T17	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4664858

1

T23

24

T24

12

T25

50

values[0x0]

all_enables

biggest_size

6025496

1

T23

118

T24

82

T25

46

values[0x1]

all_enables

biggest_size

6029825

1

T23

98

T24

82

T25

54