Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	173695791	0	0	0
ctrl_en_input_filter_rd_A	173695791	76343	0	0
intr_ctrl_en_falling_rd_A	173695791	79952	0	0
intr_ctrl_en_lvlhigh_rd_A	173695791	75069	0	0
intr_ctrl_en_lvllow_rd_A	173695791	77899	0	0
intr_ctrl_en_rising_rd_A	173695791	75955	0	0
intr_enable_rd_A	173695791	75517	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173695791	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173695791	76343	0	0
T1	26974	166	0	0
T2	0	3151	0	0
T3	0	3	0	0
T4	0	3039	0	0
T5	0	371	0	0
T6	0	962	0	0
T7	0	4	0	0
T8	0	216	0	0
T9	0	2964	0	0
T10	0	158	0	0
T11	835	0	0	0
T12	8203	0	0	0
T13	847	0	0	0
T14	6252	0	0	0
T15	6549	0	0	0
T16	1151	0	0	0
T17	17450	0	0	0
T18	184443	0	0	0
T19	1070	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173695791	79952	0	0
T1	26974	170	0	0
T2	0	3131	0	0
T4	0	3103	0	0
T5	0	420	0	0
T6	0	846	0	0
T8	0	229	0	0
T9	0	2971	0	0
T10	0	128	0	0
T11	835	0	0	0
T12	8203	0	0	0
T13	847	0	0	0
T14	6252	0	0	0
T15	6549	0	0	0
T16	1151	0	0	0
T17	17450	0	0	0
T18	184443	0	0	0
T19	1070	0	0	0
T20	0	1	0	0
T21	0	7	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173695791	75069	0	0
T1	26974	130	0	0
T2	0	3028	0	0
T3	0	4	0	0
T4	0	3065	0	0
T5	0	496	0	0
T6	0	782	0	0
T8	0	158	0	0
T9	0	3119	0	0
T11	835	0	0	0
T12	8203	0	0	0
T13	847	0	0	0
T14	6252	0	0	0
T15	6549	0	0	0
T16	1151	0	0	0
T17	17450	0	0	0
T18	184443	0	0	0
T19	1070	0	0	0
T20	0	5	0	0
T21	0	3	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173695791	77899	0	0
T1	26974	97	0	0
T2	0	3211	0	0
T3	0	1	0	0
T4	0	2990	0	0
T5	0	356	0	0
T6	0	755	0	0
T8	0	125	0	0
T9	0	3073	0	0
T11	835	0	0	0
T12	8203	0	0	0
T13	847	0	0	0
T14	6252	0	0	0
T15	6549	0	0	0
T16	1151	0	0	0
T17	17450	0	0	0
T18	184443	0	0	0
T19	1070	0	0	0
T21	0	6	0	0
T22	0	7	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173695791	75955	0	0
T1	26974	127	0	0
T2	0	3004	0	0
T3	0	4	0	0
T4	0	3254	0	0
T5	0	359	0	0
T6	0	806	0	0
T7	0	4	0	0
T8	0	151	0	0
T11	835	0	0	0
T12	8203	0	0	0
T13	847	0	0	0
T14	6252	0	0	0
T15	6549	0	0	0
T16	1151	0	0	0
T17	17450	0	0	0
T18	184443	0	0	0
T19	1070	0	0	0
T20	0	2	0	0
T21	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173695791	75517	0	0
T1	26974	155	0	0
T2	0	2997	0	0
T4	0	3125	0	0
T5	0	494	0	0
T6	0	672	0	0
T8	0	223	0	0
T9	0	3186	0	0
T10	0	107	0	0
T11	835	0	0	0
T12	8203	0	0	0
T13	847	0	0	0
T14	6252	0	0	0
T15	6549	0	0	0
T16	1151	0	0	0
T17	17450	0	0	0
T18	184443	0	0	0
T19	1070	0	0	0
T20	0	7	0	0
T21	0	1	0	0