Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	188252609	0	0	0
ctrl_en_input_filter_rd_A	188252609	64077	0	0
intr_ctrl_en_falling_rd_A	188252609	67626	0	0
intr_ctrl_en_lvlhigh_rd_A	188252609	63851	0	0
intr_ctrl_en_lvllow_rd_A	188252609	65940	0	0
intr_ctrl_en_rising_rd_A	188252609	63652	0	0
intr_enable_rd_A	188252609	65409	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188252609	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188252609	64077	0	0
T1	573331	18480	0	0
T2	28041	205	0	0
T3	8779	2	0	0
T4	167346	5876	0	0
T5	0	232	0	0
T6	0	215	0	0
T7	0	3333	0	0
T8	0	307	0	0
T9	0	1451	0	0
T10	0	172	0	0
T11	98368	0	0	0
T12	2111	0	0	0
T13	5275	0	0	0
T14	10036	0	0	0
T15	5783	0	0	0
T16	3570	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188252609	67626	0	0
T1	573331	21356	0	0
T2	28041	199	0	0
T3	8779	5	0	0
T4	167346	5952	0	0
T5	0	245	0	0
T6	0	190	0	0
T7	0	3460	0	0
T8	0	432	0	0
T9	0	1320	0	0
T11	98368	0	0	0
T12	2111	0	0	0
T13	5275	0	0	0
T14	10036	0	0	0
T15	5783	0	0	0
T16	3570	0	0	0
T17	0	18	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188252609	63851	0	0
T1	573331	19028	0	0
T2	28041	167	0	0
T3	8779	0	0	0
T4	167346	5891	0	0
T5	0	307	0	0
T6	0	204	0	0
T7	0	3533	0	0
T8	0	390	0	0
T9	0	1391	0	0
T11	98368	0	0	0
T12	2111	0	0	0
T13	5275	0	0	0
T14	10036	0	0	0
T15	5783	0	0	0
T16	3570	0	0	0
T17	0	6	0	0
T18	0	2	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188252609	65940	0	0
T1	573331	21384	0	0
T2	28041	149	0	0
T3	8779	5	0	0
T4	167346	5535	0	0
T5	0	332	0	0
T6	0	123	0	0
T7	0	3517	0	0
T8	0	431	0	0
T9	0	1212	0	0
T11	98368	0	0	0
T12	2111	0	0	0
T13	5275	0	0	0
T14	10036	0	0	0
T15	5783	0	0	0
T16	3570	0	0	0
T17	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188252609	63652	0	0
T1	573331	18544	0	0
T2	28041	159	0	0
T3	8779	1	0	0
T4	167346	5657	0	0
T5	0	260	0	0
T6	0	195	0	0
T7	0	3456	0	0
T8	0	455	0	0
T9	0	1390	0	0
T11	98368	0	0	0
T12	2111	0	0	0
T13	5275	0	0	0
T14	10036	0	0	0
T15	5783	0	0	0
T16	3570	0	0	0
T17	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188252609	65409	0	0
T1	573331	19292	0	0
T2	28041	234	0	0
T3	8779	0	0	0
T4	167346	5836	0	0
T5	0	319	0	0
T6	0	220	0	0
T7	0	3531	0	0
T8	0	350	0	0
T9	0	1304	0	0
T10	0	186	0	0
T11	98368	0	0	0
T12	2111	0	0	0
T13	5275	0	0	0
T14	10036	0	0	0
T15	5783	0	0	0
T16	3570	0	0	0
T17	0	1	0	0