Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3353570	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14732065

1

T22

224

T23

123

T24

187

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7276187	1			T22	58		T23	130		T24	117
values[0x0]	5320449	1			T22	84		T23	29		T24	57
values[0x1]	5488999	1			T22	107		T23	31		T24	58

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2586834	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15498801

1

T22

227

T23

133

T24

199

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	61632	1			T31	4		T33	622		T115	3
valid_sources[0x01]	63139	1			T22	1		T30	1		T31	2
valid_sources[0x02]	62740	1			T25	1		T31	2		T33	618
valid_sources[0x03]	229900	1			T24	23		T30	1		T31	4
valid_sources[0x04]	64498	1			T31	2		T33	589		T116	2
valid_sources[0x05]	59066	1			T31	1		T33	621		T115	5
valid_sources[0x06]	64301	1			T22	4		T31	7		T34	180
valid_sources[0x07]	60135	1			T22	3		T30	1		T31	3
valid_sources[0x08]	163702	1			T24	1		T25	1		T31	4
valid_sources[0x09]	73486	1			T25	3		T31	4		T33	595
valid_sources[0x0a]	68352	1			T25	2		T30	1		T31	4
valid_sources[0x0b]	63963	1			T31	2		T33	657		T35	5
valid_sources[0x0c]	182454	1			T31	3		T32	119442		T33	658
valid_sources[0x0d]	62760	1			T25	1		T31	6		T33	597
valid_sources[0x0e]	64468	1			T25	1		T31	2		T33	630
valid_sources[0x0f]	62210	1			T30	1		T31	1		T33	584
valid_sources[0x10]	65859	1			T30	1		T31	4		T117	10
valid_sources[0x11]	60154	1			T31	3		T33	595		T115	5
valid_sources[0x12]	65352	1			T22	5		T31	2		T33	618
valid_sources[0x13]	58813	1			T25	3		T31	3		T33	584
valid_sources[0x14]	68910	1			T22	4		T25	5		T31	7
valid_sources[0x15]	68501	1			T22	2		T25	7		T31	3
valid_sources[0x16]	66335	1			T22	1		T25	1		T31	3
valid_sources[0x17]	62155	1			T22	3		T30	1		T31	3
valid_sources[0x18]	60806	1			T22	6		T24	2		T31	1
valid_sources[0x19]	65804	1			T31	5		T117	2		T33	610
valid_sources[0x1a]	60872	1			T25	11		T30	2		T31	4
valid_sources[0x1b]	60140	1			T22	8		T31	8		T33	599
valid_sources[0x1c]	70136	1			T25	1		T31	2		T33	619
valid_sources[0x1d]	65937	1			T30	1		T31	6		T33	611
valid_sources[0x1e]	69108	1			T22	3		T30	1		T31	4
valid_sources[0x1f]	71704	1			T25	1		T31	5		T33	586
valid_sources[0x20]	64224	1			T22	1		T23	190		T31	1
valid_sources[0x21]	62113	1			T30	1		T31	3		T33	597
valid_sources[0x22]	61007	1			T22	2		T25	2		T31	7
valid_sources[0x23]	61385	1			T25	1		T30	1		T31	3
valid_sources[0x24]	61564	1			T30	1		T31	5		T33	579
valid_sources[0x25]	62917	1			T25	1		T31	7		T33	623
valid_sources[0x26]	61024	1			T26	20		T30	1		T31	3
valid_sources[0x27]	61930	1			T25	2		T31	9		T33	591
valid_sources[0x28]	63339	1			T22	8		T25	7		T31	3
valid_sources[0x29]	60606	1			T31	3		T33	625		T115	7
valid_sources[0x2a]	64110	1			T24	20		T25	6		T31	3
valid_sources[0x2b]	65160	1			T22	2		T24	13		T25	4
valid_sources[0x2c]	68712	1			T25	3		T31	6		T33	660
valid_sources[0x2d]	63324	1			T31	4		T33	570		T35	7
valid_sources[0x2e]	67775	1			T22	2		T25	10		T30	1
valid_sources[0x2f]	209154	1			T30	1		T31	6		T33	607
valid_sources[0x30]	62270	1			T25	2		T30	3		T31	6
valid_sources[0x31]	61715	1			T22	1		T25	3		T31	3
valid_sources[0x32]	59650	1			T25	2		T31	7		T33	670
valid_sources[0x33]	68742	1			T30	5		T31	4		T33	649
valid_sources[0x34]	64345	1			T24	4		T25	1		T30	2
valid_sources[0x35]	63173	1			T25	2		T30	3		T31	10
valid_sources[0x36]	64947	1			T22	4		T31	3		T33	582
valid_sources[0x37]	62501	1			T25	1		T31	3		T33	647
valid_sources[0x38]	60690	1			T30	1		T31	2		T33	618
valid_sources[0x39]	69621	1			T25	3		T30	2		T31	4
valid_sources[0x3a]	66147	1			T31	2		T33	608		T115	8
valid_sources[0x3b]	68892	1			T25	4		T31	4		T33	589
valid_sources[0x3c]	63678	1			T22	3		T25	2		T30	1
valid_sources[0x3d]	67059	1			T25	1		T30	4		T31	3
valid_sources[0x3e]	70606	1			T31	8		T33	600		T35	4
valid_sources[0x3f]	62520	1			T22	1		T25	2		T31	6
valid_sources[0x40]	63528	1			T22	8		T25	4		T28	170
valid_sources[0x41]	62894	1			T22	1		T31	4		T33	590
valid_sources[0x42]	58742	1			T25	2		T31	3		T33	604
valid_sources[0x43]	61130	1			T25	6		T31	7		T33	569
valid_sources[0x44]	64475	1			T31	2		T33	553		T115	1
valid_sources[0x45]	61011	1			T33	575		T35	6		T1	1837
valid_sources[0x46]	58150	1			T22	4		T25	1		T31	5
valid_sources[0x47]	62347	1			T22	4		T30	1		T31	3
valid_sources[0x48]	60572	1			T25	1		T30	1		T31	3
valid_sources[0x49]	59457	1			T25	1		T31	3		T33	591
valid_sources[0x4a]	62378	1			T31	3		T33	631		T35	5
valid_sources[0x4b]	62019	1			T25	1		T31	5		T33	622
valid_sources[0x4c]	66028	1			T25	1		T31	3		T33	596
valid_sources[0x4d]	60472	1			T22	3		T30	1		T31	3
valid_sources[0x4e]	68749	1			T25	4		T30	2		T31	5
valid_sources[0x4f]	59767	1			T25	2		T31	2		T117	3
valid_sources[0x50]	66003	1			T25	4		T31	4		T33	624
valid_sources[0x51]	57662	1			T22	1		T31	6		T117	1
valid_sources[0x52]	61863	1			T25	1		T27	260		T31	6
valid_sources[0x53]	63930	1			T31	9		T33	632		T35	8
valid_sources[0x54]	205986	1			T25	1		T31	4		T33	598
valid_sources[0x55]	64224	1			T31	4		T33	607		T35	6
valid_sources[0x56]	68139	1			T22	1		T25	1		T31	3
valid_sources[0x57]	66083	1			T31	4		T33	617		T118	13
valid_sources[0x58]	66908	1			T31	3		T117	14		T33	584
valid_sources[0x59]	58541	1			T31	5		T33	639		T115	1
valid_sources[0x5a]	63850	1			T22	7		T30	1		T31	2
valid_sources[0x5b]	64473	1			T30	2		T31	5		T33	573
valid_sources[0x5c]	60270	1			T22	1		T24	9		T31	4
valid_sources[0x5d]	64479	1			T31	2		T33	625		T115	13
valid_sources[0x5e]	57478	1			T31	7		T33	597		T35	6
valid_sources[0x5f]	60126	1			T30	1		T31	4		T33	630
valid_sources[0x60]	69999	1			T22	3		T25	1		T30	1
valid_sources[0x61]	65416	1			T22	9		T25	1		T31	3
valid_sources[0x62]	68465	1			T25	4		T31	2		T33	601
valid_sources[0x63]	60985	1			T31	1		T117	5		T33	604
valid_sources[0x64]	65175	1			T22	5		T31	7		T33	614
valid_sources[0x65]	174929	1			T25	2		T31	5		T117	9
valid_sources[0x66]	59229	1			T22	1		T31	2		T33	586
valid_sources[0x67]	60119	1			T30	1		T31	3		T33	640
valid_sources[0x68]	65785	1			T31	6		T33	632		T35	10
valid_sources[0x69]	60431	1			T22	5		T24	16		T25	2
valid_sources[0x6a]	60763	1			T22	1		T31	3		T33	593
valid_sources[0x6b]	61696	1			T22	3		T25	3		T31	4
valid_sources[0x6c]	67966	1			T25	1		T31	5		T33	631
valid_sources[0x6d]	66856	1			T22	5		T31	6		T33	630
valid_sources[0x6e]	61603	1			T22	2		T31	5		T33	588
valid_sources[0x6f]	61187	1			T31	2		T33	592		T35	3
valid_sources[0x70]	57868	1			T25	3		T31	2		T117	8
valid_sources[0x71]	201280	1			T31	4		T33	629		T118	5
valid_sources[0x72]	68727	1			T22	1		T25	3		T31	3
valid_sources[0x73]	66934	1			T31	9		T33	602		T35	7
valid_sources[0x74]	65850	1			T22	2		T31	3		T33	619
valid_sources[0x75]	63505	1			T25	2		T31	4		T33	611
valid_sources[0x76]	60471	1			T22	5		T25	1		T31	2
valid_sources[0x77]	63983	1			T33	636		T35	10		T116	1
valid_sources[0x78]	64009	1			T30	2		T31	8		T33	611
valid_sources[0x79]	63142	1			T29	2811		T30	1		T31	7
valid_sources[0x7a]	60528	1			T22	2		T31	3		T33	587
valid_sources[0x7b]	72378	1			T22	1		T24	7		T31	6
valid_sources[0x7c]	63629	1			T22	1		T25	5		T30	1
valid_sources[0x7d]	59673	1			T24	11		T31	5		T33	627
valid_sources[0x7e]	72694	1			T25	1		T30	1		T31	3
valid_sources[0x7f]	63308	1			T24	7		T31	2		T117	30
valid_sources[0x80]	62790	1			T24	1		T25	1		T31	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4128390

1

T22

33

T23

63

T24

72

values[0x0]

all_enables

biggest_size

5303311

1

T22

84

T23

29

T24

57

values[0x1]

all_enables

biggest_size

5300364

1

T22

107

T23

31

T24

58