Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	150141938	0	0	0
ctrl_en_input_filter_rd_A	150141938	56426	0	0
intr_ctrl_en_falling_rd_A	150141938	58969	0	0
intr_ctrl_en_lvlhigh_rd_A	150141938	56145	0	0
intr_ctrl_en_lvllow_rd_A	150141938	59974	0	0
intr_ctrl_en_rising_rd_A	150141938	55604	0	0
intr_enable_rd_A	150141938	56157	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150141938	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150141938	56426	0	0
T1	552682	17030	0	0
T2	0	233	0	0
T3	0	126	0	0
T4	0	4271	0	0
T5	0	164	0	0
T6	0	1548	0	0
T7	0	17	0	0
T8	0	77	0	0
T9	0	4	0	0
T10	0	1879	0	0
T11	603609	0	0	0
T12	4560	0	0	0
T13	3700	0	0	0
T14	2960	0	0	0
T15	3417	0	0	0
T16	5757	0	0	0
T17	4044	0	0	0
T18	4192	0	0	0
T19	3442	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150141938	58969	0	0
T1	552682	18358	0	0
T2	0	187	0	0
T3	0	125	0	0
T4	0	4182	0	0
T5	0	149	0	0
T6	0	1629	0	0
T7	0	11	0	0
T8	0	94	0	0
T9	0	2	0	0
T10	0	1807	0	0
T11	603609	0	0	0
T12	4560	0	0	0
T13	3700	0	0	0
T14	2960	0	0	0
T15	3417	0	0	0
T16	5757	0	0	0
T17	4044	0	0	0
T18	4192	0	0	0
T19	3442	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150141938	56145	0	0
T1	552682	16943	0	0
T2	0	144	0	0
T3	0	119	0	0
T4	0	3948	0	0
T5	0	174	0	0
T6	0	1630	0	0
T7	0	15	0	0
T8	0	62	0	0
T10	0	1681	0	0
T11	603609	0	0	0
T12	4560	0	0	0
T13	3700	0	0	0
T14	2960	0	0	0
T15	3417	0	0	0
T16	5757	0	0	0
T17	4044	0	0	0
T18	4192	0	0	0
T19	3442	0	0	0
T20	0	7	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150141938	59974	0	0
T1	552682	18016	0	0
T2	0	169	0	0
T3	0	158	0	0
T4	0	4399	0	0
T5	0	146	0	0
T6	0	1798	0	0
T7	0	2	0	0
T8	0	128	0	0
T10	0	1702	0	0
T11	603609	0	0	0
T12	4560	0	0	0
T13	3700	0	0	0
T14	2960	0	0	0
T15	3417	0	0	0
T16	5757	0	0	0
T17	4044	0	0	0
T18	4192	0	0	0
T19	3442	0	0	0
T21	0	3428	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150141938	55604	0	0
T1	552682	15975	0	0
T2	0	223	0	0
T3	0	162	0	0
T4	0	4150	0	0
T5	0	205	0	0
T6	0	1740	0	0
T7	0	7	0	0
T8	0	134	0	0
T10	0	1838	0	0
T11	603609	0	0	0
T12	4560	0	0	0
T13	3700	0	0	0
T14	2960	0	0	0
T15	3417	0	0	0
T16	5757	0	0	0
T17	4044	0	0	0
T18	4192	0	0	0
T19	3442	0	0	0
T20	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150141938	56157	0	0
T1	552682	16553	0	0
T2	0	194	0	0
T3	0	114	0	0
T4	0	4267	0	0
T5	0	124	0	0
T6	0	1803	0	0
T7	0	1	0	0
T8	0	104	0	0
T10	0	1737	0	0
T11	603609	0	0	0
T12	4560	0	0	0
T13	3700	0	0	0
T14	2960	0	0	0
T15	3417	0	0	0
T16	5757	0	0	0
T17	4044	0	0	0
T18	4192	0	0	0
T19	3442	0	0	0
T21	0	3309	0	0