Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3019741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13157929

1

T23

187

T24

1284

T25

140

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6547435	1			T23	97		T24	865		T25	178
values[0x0]	4740931	1			T23	71		T24	396		T25	19
values[0x1]	4889304	1			T23	71		T24	435		T25	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2331146	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13846524

1

T23

198

T24

1362

T25

154

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	63737	1			T23	1		T11	251		T17	2
valid_sources[0x01]	95884	1			T23	2		T24	8		T11	258
valid_sources[0x02]	55532	1			T23	1		T24	12		T11	309
valid_sources[0x03]	61464	1			T23	1		T24	18		T25	2
valid_sources[0x04]	54263	1			T24	18		T25	1		T11	252
valid_sources[0x05]	60604	1			T23	1		T24	2		T25	1
valid_sources[0x06]	54010	1			T24	20		T25	1		T11	265
valid_sources[0x07]	61155	1			T23	1		T24	1		T11	260
valid_sources[0x08]	61537	1			T23	1		T25	1		T11	279
valid_sources[0x09]	52833	1			T23	1		T24	15		T11	257
valid_sources[0x0a]	57492	1			T24	7		T25	3		T11	256
valid_sources[0x0b]	59194	1			T24	1		T11	282		T13	2
valid_sources[0x0c]	54574	1			T11	298		T13	4		T26	13
valid_sources[0x0d]	59275	1			T23	1		T25	1		T11	245
valid_sources[0x0e]	55769	1			T23	2		T11	308		T17	1
valid_sources[0x0f]	60565	1			T25	2		T11	279		T12	5
valid_sources[0x10]	55390	1			T23	1		T24	2		T25	2
valid_sources[0x11]	60504	1			T24	32		T25	1		T11	271
valid_sources[0x12]	64816	1			T23	1		T24	36		T11	272
valid_sources[0x13]	60863	1			T25	1		T11	264		T12	2
valid_sources[0x14]	58722	1			T23	2		T24	9		T11	243
valid_sources[0x15]	59326	1			T23	1		T24	15		T25	2
valid_sources[0x16]	57827	1			T23	1		T25	4		T11	245
valid_sources[0x17]	56038	1			T23	1		T24	2		T11	298
valid_sources[0x18]	53214	1			T23	1		T24	1		T25	2
valid_sources[0x19]	60650	1			T25	2		T11	229		T13	6
valid_sources[0x1a]	56565	1			T25	1		T11	292		T12	1
valid_sources[0x1b]	55000	1			T24	14		T11	264		T17	3
valid_sources[0x1c]	56263	1			T23	2		T24	3		T25	2
valid_sources[0x1d]	56819	1			T11	269		T12	2		T17	4
valid_sources[0x1e]	52741	1			T24	1		T25	1		T11	239
valid_sources[0x1f]	52506	1			T24	4		T25	1		T11	264
valid_sources[0x20]	61619	1			T23	1		T24	5		T11	283
valid_sources[0x21]	62321	1			T24	17		T11	270		T12	1
valid_sources[0x22]	71940	1			T24	22		T11	297		T17	3
valid_sources[0x23]	60218	1			T23	1		T24	22		T11	281
valid_sources[0x24]	53014	1			T11	267		T26	20		T102	5
valid_sources[0x25]	55016	1			T25	2		T11	275		T17	2
valid_sources[0x26]	58582	1			T24	4		T25	1		T11	287
valid_sources[0x27]	70355	1			T24	1		T11	233		T12	2
valid_sources[0x28]	69285	1			T24	21		T11	251		T26	8
valid_sources[0x29]	59889	1			T24	7		T25	1		T11	288
valid_sources[0x2a]	57127	1			T23	1		T11	275		T12	6
valid_sources[0x2b]	53110	1			T24	13		T11	250		T12	1
valid_sources[0x2c]	53858	1			T24	12		T25	2		T11	275
valid_sources[0x2d]	58103	1			T23	2		T24	1		T11	275
valid_sources[0x2e]	59127	1			T23	1		T24	15		T11	251
valid_sources[0x2f]	58958	1			T23	1		T11	227		T17	3
valid_sources[0x30]	61007	1			T23	1		T24	2		T25	1
valid_sources[0x31]	58717	1			T23	3		T24	9		T25	1
valid_sources[0x32]	52170	1			T24	12		T25	1		T11	311
valid_sources[0x33]	51962	1			T23	2		T24	2		T11	284
valid_sources[0x34]	60205	1			T23	2		T24	2		T25	4
valid_sources[0x35]	57707	1			T23	2		T24	7		T11	270
valid_sources[0x36]	146812	1			T24	3		T25	1		T11	281
valid_sources[0x37]	55086	1			T23	2		T24	10		T11	239
valid_sources[0x38]	55402	1			T23	2		T11	240		T12	8
valid_sources[0x39]	55104	1			T25	2		T11	300		T26	18
valid_sources[0x3a]	133626	1			T24	25		T25	1		T11	287
valid_sources[0x3b]	54995	1			T24	2		T11	237		T12	1
valid_sources[0x3c]	56560	1			T23	2		T24	10		T11	328
valid_sources[0x3d]	59652	1			T24	3		T11	287		T12	7
valid_sources[0x3e]	59583	1			T23	1		T24	3		T11	276
valid_sources[0x3f]	56888	1			T24	2		T25	4		T11	239
valid_sources[0x40]	59009	1			T23	2		T24	1		T11	256
valid_sources[0x41]	63482	1			T23	1		T25	1		T11	276
valid_sources[0x42]	56755	1			T23	4		T24	25		T11	259
valid_sources[0x43]	62536	1			T23	3		T24	13		T11	204
valid_sources[0x44]	61506	1			T23	1		T11	289		T12	2
valid_sources[0x45]	62440	1			T24	7		T25	1		T11	246
valid_sources[0x46]	55429	1			T24	10		T25	2		T11	254
valid_sources[0x47]	57097	1			T23	1		T24	8		T11	279
valid_sources[0x48]	56815	1			T24	12		T11	322		T13	5
valid_sources[0x49]	57492	1			T23	2		T25	1		T11	249
valid_sources[0x4a]	58958	1			T23	2		T11	247		T17	2
valid_sources[0x4b]	60779	1			T24	7		T11	252		T12	2
valid_sources[0x4c]	54671	1			T24	6		T25	1		T11	236
valid_sources[0x4d]	54185	1			T24	13		T11	236		T12	4
valid_sources[0x4e]	59098	1			T23	1		T24	3		T25	2
valid_sources[0x4f]	61699	1			T23	1		T24	7		T11	277
valid_sources[0x50]	57514	1			T23	2		T24	21		T25	1
valid_sources[0x51]	136904	1			T23	2		T25	2		T11	264
valid_sources[0x52]	201160	1			T23	2		T24	12		T11	284
valid_sources[0x53]	62251	1			T23	1		T24	11		T11	246
valid_sources[0x54]	58827	1			T24	4		T25	1		T11	306
valid_sources[0x55]	57928	1			T23	1		T24	7		T25	2
valid_sources[0x56]	53185	1			T25	1		T11	253		T12	5
valid_sources[0x57]	57989	1			T24	4		T11	242		T12	1
valid_sources[0x58]	65316	1			T11	318		T12	1		T17	6
valid_sources[0x59]	58226	1			T23	6		T24	8		T11	293
valid_sources[0x5a]	55602	1			T24	8		T25	1		T11	277
valid_sources[0x5b]	53495	1			T25	2		T11	317		T13	4
valid_sources[0x5c]	52775	1			T24	7		T11	242		T26	7
valid_sources[0x5d]	120013	1			T23	1		T24	1		T25	1
valid_sources[0x5e]	60773	1			T23	2		T24	7		T25	1
valid_sources[0x5f]	58878	1			T24	10		T25	2		T11	286
valid_sources[0x60]	57853	1			T23	1		T24	2		T11	249
valid_sources[0x61]	62895	1			T11	258		T12	4		T13	1
valid_sources[0x62]	63260	1			T25	1		T11	294		T13	8
valid_sources[0x63]	197843	1			T24	16		T11	282		T12	8
valid_sources[0x64]	56886	1			T23	1		T24	3		T11	256
valid_sources[0x65]	58707	1			T25	2		T11	256		T12	2
valid_sources[0x66]	57402	1			T24	2		T25	1		T11	330
valid_sources[0x67]	65318	1			T23	1		T11	230		T17	11
valid_sources[0x68]	55731	1			T24	2		T25	2		T11	312
valid_sources[0x69]	58885	1			T23	1		T11	253		T13	4
valid_sources[0x6a]	60157	1			T24	6		T25	1		T11	255
valid_sources[0x6b]	51531	1			T24	20		T11	347		T13	6
valid_sources[0x6c]	56279	1			T23	1		T25	1		T11	243
valid_sources[0x6d]	52244	1			T23	3		T11	245		T13	2
valid_sources[0x6e]	59098	1			T24	2		T11	296		T12	4
valid_sources[0x6f]	55520	1			T24	10		T25	2		T11	295
valid_sources[0x70]	63944	1			T23	2		T25	1		T11	300
valid_sources[0x71]	56964	1			T24	2		T11	226		T12	5
valid_sources[0x72]	59300	1			T23	1		T25	1		T11	267
valid_sources[0x73]	60441	1			T23	2		T24	15		T25	1
valid_sources[0x74]	56210	1			T24	10		T25	1		T11	282
valid_sources[0x75]	53209	1			T23	2		T24	7		T25	3
valid_sources[0x76]	61197	1			T24	2		T11	251		T13	2
valid_sources[0x77]	53262	1			T23	1		T24	30		T25	1
valid_sources[0x78]	56467	1			T23	2		T24	29		T25	2
valid_sources[0x79]	53778	1			T23	1		T24	9		T25	1
valid_sources[0x7a]	58759	1			T23	1		T25	1		T11	286
valid_sources[0x7b]	54844	1			T25	1		T11	263		T17	9
valid_sources[0x7c]	52745	1			T25	2		T11	216		T17	1
valid_sources[0x7d]	54497	1			T23	1		T11	271		T12	1
valid_sources[0x7e]	54406	1			T24	17		T25	1		T11	220
valid_sources[0x7f]	57315	1			T23	1		T11	237		T13	3
valid_sources[0x80]	63663	1			T23	2		T24	7		T11	329

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3710297

1

T23

45

T24

453

T25

98

values[0x0]

all_enables

biggest_size

4725545

1

T23

71

T24

396

T25

19

values[0x1]

all_enables

biggest_size

4722087

1

T23

71

T24

435

T25

23