Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	138820969	0	0	0
ctrl_en_input_filter_rd_A	138820969	104634	0	0
intr_ctrl_en_falling_rd_A	138820969	107302	0	0
intr_ctrl_en_lvlhigh_rd_A	138820969	106539	0	0
intr_ctrl_en_lvllow_rd_A	138820969	107056	0	0
intr_ctrl_en_rising_rd_A	138820969	104784	0	0
intr_enable_rd_A	138820969	104403	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138820969	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138820969	104634	0	0
T1	818435	2764	0	0
T2	0	2827	0	0
T3	0	1	0	0
T4	0	12515	0	0
T5	0	4319	0	0
T6	0	4431	0	0
T7	0	312	0	0
T8	0	655	0	0
T9	0	113	0	0
T10	0	53	0	0
T11	687220	0	0	0
T12	3897	0	0	0
T13	2893	0	0	0
T14	3634	0	0	0
T15	2463	0	0	0
T16	771	0	0	0
T17	3812	0	0	0
T18	9543	0	0	0
T19	131909	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138820969	107302	0	0
T1	818435	2774	0	0
T2	0	2940	0	0
T4	0	13428	0	0
T5	0	4522	0	0
T6	0	4551	0	0
T7	0	298	0	0
T8	0	558	0	0
T9	0	154	0	0
T10	0	80	0	0
T11	687220	0	0	0
T12	3897	0	0	0
T13	2893	0	0	0
T14	3634	0	0	0
T15	2463	0	0	0
T16	771	0	0	0
T17	3812	0	0	0
T18	9543	0	0	0
T19	131909	0	0	0
T20	0	176	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138820969	106539	0	0
T1	818435	2723	0	0
T2	0	3000	0	0
T3	0	5	0	0
T4	0	12526	0	0
T5	0	4526	0	0
T6	0	4493	0	0
T7	0	320	0	0
T8	0	595	0	0
T9	0	118	0	0
T10	0	70	0	0
T11	687220	0	0	0
T12	3897	0	0	0
T13	2893	0	0	0
T14	3634	0	0	0
T15	2463	0	0	0
T16	771	0	0	0
T17	3812	0	0	0
T18	9543	0	0	0
T19	131909	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138820969	107056	0	0
T1	818435	2963	0	0
T2	0	2923	0	0
T3	0	7	0	0
T4	0	13220	0	0
T5	0	4212	0	0
T6	0	4696	0	0
T7	0	379	0	0
T8	0	621	0	0
T9	0	139	0	0
T11	687220	0	0	0
T12	3897	0	0	0
T13	2893	0	0	0
T14	3634	0	0	0
T15	2463	0	0	0
T16	771	0	0	0
T17	3812	0	0	0
T18	9543	0	0	0
T19	131909	0	0	0
T21	0	3	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138820969	104784	0	0
T1	818435	2902	0	0
T2	0	2760	0	0
T4	0	12564	0	0
T5	0	4365	0	0
T6	0	4278	0	0
T7	0	330	0	0
T8	0	661	0	0
T9	0	151	0	0
T10	0	75	0	0
T11	687220	0	0	0
T12	3897	0	0	0
T13	2893	0	0	0
T14	3634	0	0	0
T15	2463	0	0	0
T16	771	0	0	0
T17	3812	0	0	0
T18	9543	0	0	0
T19	131909	0	0	0
T20	0	139	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138820969	104403	0	0
T1	818435	2785	0	0
T2	0	2697	0	0
T4	0	12311	0	0
T5	0	4507	0	0
T6	0	4553	0	0
T7	0	351	0	0
T8	0	638	0	0
T9	0	136	0	0
T10	0	113	0	0
T11	687220	0	0	0
T12	3897	0	0	0
T13	2893	0	0	0
T14	3634	0	0	0
T15	2463	0	0	0
T16	771	0	0	0
T17	3812	0	0	0
T18	9543	0	0	0
T19	131909	0	0	0
T22	0	2	0	0