Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3075681	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13379277

1

T24

227

T25

314

T26

3077

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6662371	1			T24	62		T25	67		T26	4796
values[0x0]	4821357	1			T24	95		T25	133		T26	357
values[0x1]	4971230	1			T24	101		T25	147		T26	348

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2375073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14079885

1

T24

233

T25

319

T26

3553

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56443	1			T26	18		T27	2		T28	7
valid_sources[0x01]	58636	1			T25	2		T26	10		T27	3
valid_sources[0x02]	59202	1			T26	18		T27	1		T28	27
valid_sources[0x03]	58119	1			T25	4		T26	34		T27	3
valid_sources[0x04]	62735	1			T25	2		T26	17		T27	1
valid_sources[0x05]	59800	1			T26	23		T27	4		T28	17
valid_sources[0x06]	58405	1			T26	24		T27	1		T28	12
valid_sources[0x07]	62629	1			T25	1		T26	21		T27	1
valid_sources[0x08]	62132	1			T25	6		T26	10		T27	6
valid_sources[0x09]	62238	1			T25	2		T26	36		T27	4
valid_sources[0x0a]	61525	1			T25	4		T26	18		T27	3
valid_sources[0x0b]	59900	1			T26	32		T27	2		T28	19
valid_sources[0x0c]	57830	1			T26	28		T27	3		T28	10
valid_sources[0x0d]	62071	1			T26	30		T27	2		T28	10
valid_sources[0x0e]	59767	1			T26	16		T28	17		T30	13
valid_sources[0x0f]	60126	1			T25	1		T26	18		T27	4
valid_sources[0x10]	60650	1			T26	10		T28	11		T30	21
valid_sources[0x11]	58852	1			T25	2		T26	20		T27	8
valid_sources[0x12]	58453	1			T25	1		T26	20		T27	4
valid_sources[0x13]	56401	1			T26	15		T27	2		T28	23
valid_sources[0x14]	59413	1			T25	3		T26	24		T27	2
valid_sources[0x15]	62904	1			T25	2		T26	28		T27	2
valid_sources[0x16]	62003	1			T25	2		T26	33		T27	2
valid_sources[0x17]	155760	1			T26	21		T27	2		T28	19
valid_sources[0x18]	56519	1			T25	1		T26	7		T27	2
valid_sources[0x19]	59823	1			T25	4		T26	22		T27	3
valid_sources[0x1a]	57727	1			T26	31		T27	3		T28	21
valid_sources[0x1b]	60268	1			T26	22		T27	1		T28	18
valid_sources[0x1c]	60916	1			T26	30		T27	7		T28	18
valid_sources[0x1d]	64182	1			T26	20		T27	2		T28	12
valid_sources[0x1e]	58668	1			T26	29		T27	4		T28	15
valid_sources[0x1f]	58440	1			T26	22		T27	2		T28	11
valid_sources[0x20]	61446	1			T26	17		T27	1		T28	18
valid_sources[0x21]	84564	1			T25	2		T26	23		T27	1
valid_sources[0x22]	59201	1			T25	3		T26	15		T27	5
valid_sources[0x23]	63344	1			T26	16		T27	1		T28	13
valid_sources[0x24]	60045	1			T25	2		T26	18		T27	3
valid_sources[0x25]	62330	1			T25	1		T26	28		T27	4
valid_sources[0x26]	61739	1			T25	1		T26	17		T27	1
valid_sources[0x27]	58233	1			T26	16		T27	1		T28	12
valid_sources[0x28]	59611	1			T25	1		T26	18		T27	3
valid_sources[0x29]	66029	1			T25	3		T26	15		T27	7
valid_sources[0x2a]	57986	1			T26	15		T28	10		T30	8
valid_sources[0x2b]	56621	1			T26	22		T27	3		T28	16
valid_sources[0x2c]	60212	1			T25	2		T26	27		T27	3
valid_sources[0x2d]	59601	1			T25	4		T26	28		T27	2
valid_sources[0x2e]	62947	1			T25	2		T26	14		T28	21
valid_sources[0x2f]	57221	1			T25	1		T26	22		T27	5
valid_sources[0x30]	64317	1			T26	29		T27	3		T28	10
valid_sources[0x31]	60051	1			T26	31		T27	3		T28	12
valid_sources[0x32]	66341	1			T26	26		T27	2		T28	19
valid_sources[0x33]	61479	1			T26	24		T27	5		T28	17
valid_sources[0x34]	65080	1			T25	2		T26	23		T27	4
valid_sources[0x35]	59495	1			T26	13		T27	2		T28	13
valid_sources[0x36]	56064	1			T25	5		T26	21		T27	2
valid_sources[0x37]	59088	1			T25	4		T26	21		T27	1
valid_sources[0x38]	58472	1			T25	2		T26	19		T27	2
valid_sources[0x39]	55905	1			T25	3		T26	33		T28	17
valid_sources[0x3a]	58970	1			T26	23		T27	1		T28	13
valid_sources[0x3b]	57990	1			T25	3		T26	23		T28	23
valid_sources[0x3c]	59692	1			T26	15		T27	2		T28	20
valid_sources[0x3d]	56681	1			T25	4		T26	32		T27	3
valid_sources[0x3e]	57906	1			T26	14		T27	1		T28	24
valid_sources[0x3f]	61421	1			T25	3		T26	30		T27	3
valid_sources[0x40]	62015	1			T25	4		T26	15		T27	3
valid_sources[0x41]	59093	1			T25	3		T26	27		T27	1
valid_sources[0x42]	59374	1			T26	20		T27	2		T28	14
valid_sources[0x43]	61600	1			T26	19		T28	18		T30	16
valid_sources[0x44]	171884	1			T25	2		T26	29		T27	5
valid_sources[0x45]	60945	1			T25	2		T26	19		T27	2
valid_sources[0x46]	60185	1			T26	25		T27	2		T28	18
valid_sources[0x47]	65717	1			T25	1		T26	27		T27	1
valid_sources[0x48]	60981	1			T26	7		T27	4		T28	17
valid_sources[0x49]	57598	1			T25	1		T26	17		T27	2
valid_sources[0x4a]	63772	1			T26	17		T27	4		T28	19
valid_sources[0x4b]	62069	1			T26	17		T27	1		T28	12
valid_sources[0x4c]	62635	1			T26	25		T27	3		T28	17
valid_sources[0x4d]	59377	1			T26	15		T28	18		T30	9
valid_sources[0x4e]	65438	1			T26	19		T27	3		T28	19
valid_sources[0x4f]	59560	1			T25	1		T26	16		T27	3
valid_sources[0x50]	60492	1			T25	5		T26	18		T28	14
valid_sources[0x51]	114530	1			T25	1		T26	19		T28	20
valid_sources[0x52]	58707	1			T25	4		T26	18		T27	3
valid_sources[0x53]	57262	1			T26	12		T27	1		T28	12
valid_sources[0x54]	58051	1			T26	27		T27	2		T28	16
valid_sources[0x55]	60692	1			T25	2		T26	37		T27	6
valid_sources[0x56]	59618	1			T26	13		T27	2		T28	15
valid_sources[0x57]	59213	1			T25	2		T26	19		T27	3
valid_sources[0x58]	59486	1			T25	2		T26	19		T27	6
valid_sources[0x59]	60724	1			T25	4		T26	20		T27	1
valid_sources[0x5a]	129299	1			T25	1		T26	20		T27	1
valid_sources[0x5b]	58210	1			T26	29		T28	15		T30	5
valid_sources[0x5c]	59721	1			T25	3		T26	22		T27	1
valid_sources[0x5d]	58594	1			T26	24		T27	1		T28	24
valid_sources[0x5e]	59932	1			T25	1		T26	18		T27	1
valid_sources[0x5f]	59067	1			T25	4		T26	18		T27	4
valid_sources[0x60]	60880	1			T25	5		T26	26		T27	4
valid_sources[0x61]	59452	1			T25	4		T26	22		T27	8
valid_sources[0x62]	60797	1			T26	12		T27	2		T28	26
valid_sources[0x63]	63084	1			T26	9		T27	2		T28	13
valid_sources[0x64]	59711	1			T25	4		T26	15		T27	4
valid_sources[0x65]	58117	1			T25	2		T26	33		T27	1
valid_sources[0x66]	62301	1			T26	22		T28	12		T30	12
valid_sources[0x67]	58044	1			T25	1		T26	17		T27	4
valid_sources[0x68]	60587	1			T26	15		T28	17		T30	18
valid_sources[0x69]	59450	1			T25	2		T26	33		T27	2
valid_sources[0x6a]	58197	1			T25	1		T26	13		T27	3
valid_sources[0x6b]	56623	1			T26	22		T27	1		T28	22
valid_sources[0x6c]	59051	1			T25	3		T26	16		T27	3
valid_sources[0x6d]	60372	1			T26	18		T28	11		T30	19
valid_sources[0x6e]	63106	1			T26	31		T27	2		T28	18
valid_sources[0x6f]	62286	1			T25	1		T26	15		T27	3
valid_sources[0x70]	61295	1			T25	2		T26	20		T27	1
valid_sources[0x71]	59362	1			T26	11		T27	4		T28	18
valid_sources[0x72]	58797	1			T25	3		T26	15		T27	1
valid_sources[0x73]	63478	1			T25	2		T26	9		T27	5
valid_sources[0x74]	61338	1			T25	1		T26	25		T27	5
valid_sources[0x75]	63038	1			T25	6		T26	40		T28	13
valid_sources[0x76]	60512	1			T25	2		T26	21		T27	5
valid_sources[0x77]	66179	1			T25	1		T26	20		T27	3
valid_sources[0x78]	72791	1			T25	1		T26	18		T27	3
valid_sources[0x79]	63555	1			T25	1		T26	22		T27	1
valid_sources[0x7a]	60552	1			T26	27		T27	3		T28	27
valid_sources[0x7b]	60320	1			T25	2		T26	31		T27	3
valid_sources[0x7c]	65345	1			T25	2		T26	21		T27	5
valid_sources[0x7d]	59808	1			T26	17		T27	3		T28	21
valid_sources[0x7e]	55522	1			T26	25		T28	15		T30	15
valid_sources[0x7f]	59331	1			T26	14		T27	3		T28	12
valid_sources[0x80]	66138	1			T25	2		T26	29		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3770739

1

T24

31

T25

34

T26

2372

values[0x0]

all_enables

biggest_size

4805703

1

T24

95

T25

133

T26

357

values[0x1]

all_enables

biggest_size

4802835

1

T24

101

T25

147

T26

348