Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	137907502	0	0	0
ctrl_en_input_filter_rd_A	137907502	115075	0	0
intr_ctrl_en_falling_rd_A	137907502	121100	0	0
intr_ctrl_en_lvlhigh_rd_A	137907502	116472	0	0
intr_ctrl_en_lvllow_rd_A	137907502	121190	0	0
intr_ctrl_en_rising_rd_A	137907502	115184	0	0
intr_enable_rd_A	137907502	115958	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137907502	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137907502	115075	0	0
T1	29719	199	0	0
T2	0	2974	0	0
T3	0	1301	0	0
T4	0	6	0	0
T5	0	4	0	0
T6	0	243	0	0
T7	0	64	0	0
T8	0	5	0	0
T9	0	2	0	0
T10	0	188	0	0
T11	304493	0	0	0
T12	1902	0	0	0
T13	3203	0	0	0
T14	4386	0	0	0
T15	6113	0	0	0
T16	4335	0	0	0
T17	143432	0	0	0
T18	4993	0	0	0
T19	3800	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137907502	121100	0	0
T1	29719	263	0	0
T2	0	2917	0	0
T3	0	1165	0	0
T5	0	9	0	0
T6	0	133	0	0
T7	0	112	0	0
T8	0	6	0	0
T10	0	225	0	0
T11	304493	0	0	0
T12	1902	0	0	0
T13	3203	0	0	0
T14	4386	0	0	0
T15	6113	0	0	0
T16	4335	0	0	0
T17	143432	0	0	0
T18	4993	0	0	0
T19	3800	0	0	0
T20	0	7	0	0
T21	0	4	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137907502	116472	0	0
T1	29719	210	0	0
T2	0	2808	0	0
T3	0	1168	0	0
T6	0	166	0	0
T7	0	106	0	0
T8	0	4	0	0
T10	0	191	0	0
T11	304493	0	0	0
T12	1902	0	0	0
T13	3203	0	0	0
T14	4386	0	0	0
T15	6113	0	0	0
T16	4335	0	0	0
T17	143432	0	0	0
T18	4993	0	0	0
T19	3800	0	0	0
T20	0	10	0	0
T22	0	3	0	0
T23	0	218	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137907502	121190	0	0
T1	29719	240	0	0
T2	0	2675	0	0
T3	0	1307	0	0
T4	0	1	0	0
T5	0	1	0	0
T6	0	130	0	0
T7	0	92	0	0
T9	0	26	0	0
T11	304493	0	0	0
T12	1902	0	0	0
T13	3203	0	0	0
T14	4386	0	0	0
T15	6113	0	0	0
T16	4335	0	0	0
T17	143432	0	0	0
T18	4993	0	0	0
T19	3800	0	0	0
T20	0	13	0	0
T21	0	5	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137907502	115184	0	0
T1	29719	174	0	0
T2	0	3057	0	0
T3	0	1179	0	0
T6	0	146	0	0
T7	0	131	0	0
T8	0	9	0	0
T9	0	2	0	0
T10	0	281	0	0
T11	304493	0	0	0
T12	1902	0	0	0
T13	3203	0	0	0
T14	4386	0	0	0
T15	6113	0	0	0
T16	4335	0	0	0
T17	143432	0	0	0
T18	4993	0	0	0
T19	3800	0	0	0
T20	0	3	0	0
T21	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137907502	115958	0	0
T1	29719	226	0	0
T2	0	2933	0	0
T3	0	1213	0	0
T4	0	5	0	0
T5	0	7	0	0
T6	0	119	0	0
T7	0	77	0	0
T10	0	161	0	0
T11	304493	0	0	0
T12	1902	0	0	0
T13	3203	0	0	0
T14	4386	0	0	0
T15	6113	0	0	0
T16	4335	0	0	0
T17	143432	0	0	0
T18	4993	0	0	0
T19	3800	0	0	0
T20	0	14	0	0
T21	0	1	0	0