Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	189629124	0	0	0
ctrl_en_input_filter_rd_A	189629124	115336	0	0
intr_ctrl_en_falling_rd_A	189629124	119470	0	0
intr_ctrl_en_lvlhigh_rd_A	189629124	113650	0	0
intr_ctrl_en_lvllow_rd_A	189629124	119158	0	0
intr_ctrl_en_rising_rd_A	189629124	114855	0	0
intr_enable_rd_A	189629124	114509	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189629124	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189629124	115336	0	0
T1	14205	78	0	0
T2	105553	3456	0	0
T3	0	136	0	0
T4	0	165	0	0
T5	0	42	0	0
T6	0	4425	0	0
T7	0	71	0	0
T8	0	10	0	0
T9	0	3223	0	0
T10	0	2291	0	0
T11	13650	0	0	0
T12	4554	0	0	0
T13	3318	0	0	0
T14	3384	0	0	0
T15	3046	0	0	0
T16	9070	0	0	0
T17	15850	0	0	0
T18	1729	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189629124	119470	0	0
T1	14205	60	0	0
T2	105553	3516	0	0
T3	0	161	0	0
T4	0	120	0	0
T5	0	48	0	0
T6	0	4610	0	0
T7	0	78	0	0
T9	0	3177	0	0
T10	0	2234	0	0
T11	13650	0	0	0
T12	4554	0	0	0
T13	3318	0	0	0
T14	3384	0	0	0
T15	3046	0	0	0
T16	9070	0	0	0
T17	15850	0	0	0
T18	1729	0	0	0
T19	0	2	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189629124	113650	0	0
T1	14205	68	0	0
T2	105553	3578	0	0
T3	0	188	0	0
T4	0	126	0	0
T5	0	45	0	0
T6	0	4586	0	0
T7	0	76	0	0
T8	0	4	0	0
T9	0	3161	0	0
T10	0	2225	0	0
T11	13650	0	0	0
T12	4554	0	0	0
T13	3318	0	0	0
T14	3384	0	0	0
T15	3046	0	0	0
T16	9070	0	0	0
T17	15850	0	0	0
T18	1729	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189629124	119158	0	0
T1	14205	68	0	0
T2	105553	3350	0	0
T3	0	182	0	0
T4	0	140	0	0
T5	0	32	0	0
T6	0	4740	0	0
T7	0	108	0	0
T8	0	9	0	0
T9	0	3186	0	0
T11	13650	0	0	0
T12	4554	0	0	0
T13	3318	0	0	0
T14	3384	0	0	0
T15	3046	0	0	0
T16	9070	0	0	0
T17	15850	0	0	0
T18	1729	0	0	0
T19	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189629124	114855	0	0
T1	14205	33	0	0
T2	105553	3613	0	0
T3	0	152	0	0
T4	0	123	0	0
T5	0	49	0	0
T6	0	4178	0	0
T7	0	125	0	0
T8	0	3	0	0
T9	0	2998	0	0
T11	13650	0	0	0
T12	4554	0	0	0
T13	3318	0	0	0
T14	3384	0	0	0
T15	3046	0	0	0
T16	9070	0	0	0
T17	15850	0	0	0
T18	1729	0	0	0
T19	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189629124	114509	0	0
T1	14205	60	0	0
T2	105553	3474	0	0
T3	0	258	0	0
T4	0	179	0	0
T5	0	52	0	0
T6	0	4605	0	0
T7	0	118	0	0
T8	0	3	0	0
T9	0	2980	0	0
T10	0	2222	0	0
T11	13650	0	0	0
T12	4554	0	0	0
T13	3318	0	0	0
T14	3384	0	0	0
T15	3046	0	0	0
T16	9070	0	0	0
T17	15850	0	0	0
T18	1729	0	0	0