Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3248838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14127721

1

T23

1343

T24

425

T25

218

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7032041	1			T23	2066		T24	99		T25	43
values[0x0]	5092617	1			T23	167		T24	203		T25	88
values[0x1]	5251901	1			T23	129		T24	181		T25	109

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2509076	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14867483

1

T23

1530

T24

439

T25

221

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	62513	1			T24	2		T1	7		T11	1
valid_sources[0x01]	65073	1			T24	7		T1	4		T11	1
valid_sources[0x02]	67728	1			T24	3		T25	1		T1	4
valid_sources[0x03]	65018	1			T1	4		T11	1		T13	2
valid_sources[0x04]	65281	1			T24	2		T1	2		T11	2
valid_sources[0x05]	63762	1			T1	2		T11	2		T13	5
valid_sources[0x06]	60958	1			T24	4		T1	3		T11	2
valid_sources[0x07]	63086	1			T1	1		T11	3		T13	2
valid_sources[0x08]	67876	1			T24	4		T2	2		T14	543
valid_sources[0x09]	62922	1			T1	5		T12	1		T13	5
valid_sources[0x0a]	62736	1			T1	7		T11	3		T13	4
valid_sources[0x0b]	60211	1			T24	1		T11	2		T13	3
valid_sources[0x0c]	69036	1			T24	3		T25	5		T11	1
valid_sources[0x0d]	63018	1			T24	3		T25	3		T11	1
valid_sources[0x0e]	63152	1			T24	4		T25	2		T1	7
valid_sources[0x0f]	132921	1			T24	5		T1	1		T11	1
valid_sources[0x10]	63562	1			T24	7		T1	4		T11	2
valid_sources[0x11]	61629	1			T25	4		T11	3		T12	1
valid_sources[0x12]	68970	1			T24	1		T1	2		T12	4
valid_sources[0x13]	64352	1			T24	8		T1	3		T14	537
valid_sources[0x14]	67902	1			T1	6		T11	2		T13	3
valid_sources[0x15]	62783	1			T24	2		T1	9		T11	1
valid_sources[0x16]	63274	1			T24	5		T11	1		T12	2
valid_sources[0x17]	68979	1			T1	2		T11	2		T13	4
valid_sources[0x18]	66235	1			T1	1		T11	2		T12	1
valid_sources[0x19]	69169	1			T25	1		T1	5		T11	4
valid_sources[0x1a]	61217	1			T24	6		T11	3		T13	6
valid_sources[0x1b]	60999	1			T1	2		T12	1		T13	5
valid_sources[0x1c]	60434	1			T24	4		T25	12		T1	7
valid_sources[0x1d]	63508	1			T24	2		T1	1		T11	1
valid_sources[0x1e]	65052	1			T1	3		T11	2		T13	2
valid_sources[0x1f]	60299	1			T1	4		T11	2		T13	1
valid_sources[0x20]	63897	1			T24	6		T1	5		T11	1
valid_sources[0x21]	61883	1			T11	1		T13	4		T2	2
valid_sources[0x22]	67566	1			T24	3		T25	1		T11	1
valid_sources[0x23]	61260	1			T24	1		T1	2		T11	1
valid_sources[0x24]	63854	1			T25	4		T13	6		T2	1
valid_sources[0x25]	66739	1			T1	1		T11	2		T13	4
valid_sources[0x26]	58560	1			T24	6		T11	1		T13	6
valid_sources[0x27]	71568	1			T24	1		T1	3		T11	1
valid_sources[0x28]	60068	1			T24	2		T25	17		T1	2
valid_sources[0x29]	60576	1			T25	2		T1	7		T11	2
valid_sources[0x2a]	65803	1			T24	2		T11	1		T12	1
valid_sources[0x2b]	63485	1			T24	4		T25	1		T1	10
valid_sources[0x2c]	64185	1			T1	1		T11	1		T12	2
valid_sources[0x2d]	58916	1			T25	13		T1	8		T11	1
valid_sources[0x2e]	65021	1			T11	1		T13	3		T14	551
valid_sources[0x2f]	59760	1			T11	3		T13	5		T2	5
valid_sources[0x30]	58568	1			T24	4		T25	1		T2	3
valid_sources[0x31]	65797	1			T24	3		T1	9		T11	1
valid_sources[0x32]	61983	1			T24	3		T1	1		T11	2
valid_sources[0x33]	57966	1			T24	5		T1	1		T11	2
valid_sources[0x34]	65379	1			T24	2		T1	2		T11	2
valid_sources[0x35]	65844	1			T1	1		T12	1		T13	1
valid_sources[0x36]	66229	1			T25	12		T11	1		T13	4
valid_sources[0x37]	65512	1			T11	3		T13	4		T14	521
valid_sources[0x38]	65111	1			T24	5		T1	1		T11	2
valid_sources[0x39]	66403	1			T24	5		T11	1		T13	1
valid_sources[0x3a]	61495	1			T1	2		T13	4		T14	545
valid_sources[0x3b]	173937	1			T24	3		T1	4		T11	2
valid_sources[0x3c]	64398	1			T24	9		T1	3		T11	1
valid_sources[0x3d]	65432	1			T1	1		T11	1		T14	557
valid_sources[0x3e]	63378	1			T25	9		T1	6		T11	3
valid_sources[0x3f]	67748	1			T24	2		T1	1		T11	2
valid_sources[0x40]	63127	1			T11	2		T2	16		T14	522
valid_sources[0x41]	64980	1			T24	5		T1	4		T11	1
valid_sources[0x42]	59565	1			T24	1		T1	7		T11	1
valid_sources[0x43]	63021	1			T25	8		T1	1		T11	2
valid_sources[0x44]	64274	1			T25	7		T13	2		T14	581
valid_sources[0x45]	59625	1			T24	1		T1	4		T13	4
valid_sources[0x46]	59023	1			T1	1		T11	2		T13	1
valid_sources[0x47]	61866	1			T11	3		T13	9		T2	2
valid_sources[0x48]	67594	1			T24	1		T1	3		T11	1
valid_sources[0x49]	65755	1			T1	4		T12	2		T13	3
valid_sources[0x4a]	57642	1			T24	4		T25	2		T13	3
valid_sources[0x4b]	70873	1			T1	2		T11	1		T13	8
valid_sources[0x4c]	67186	1			T1	2		T11	3		T12	3
valid_sources[0x4d]	71207	1			T11	1		T13	3		T2	5
valid_sources[0x4e]	60452	1			T24	4		T25	5		T13	5
valid_sources[0x4f]	74243	1			T24	2		T25	13		T11	2
valid_sources[0x50]	63361	1			T13	6		T14	567		T47	2
valid_sources[0x51]	66480	1			T24	1		T1	1		T11	4
valid_sources[0x52]	61461	1			T1	7		T11	2		T13	1
valid_sources[0x53]	67586	1			T24	1		T1	11		T11	3
valid_sources[0x54]	61228	1			T1	7		T11	3		T14	581
valid_sources[0x55]	60110	1			T24	1		T1	15		T13	4
valid_sources[0x56]	59911	1			T24	2		T1	8		T11	4
valid_sources[0x57]	59607	1			T25	1		T13	1		T14	576
valid_sources[0x58]	59487	1			T24	9		T25	2		T11	1
valid_sources[0x59]	57906	1			T24	7		T12	1		T14	560
valid_sources[0x5a]	63699	1			T1	10		T11	6		T13	2
valid_sources[0x5b]	58543	1			T25	3		T1	3		T11	2
valid_sources[0x5c]	64600	1			T24	1		T1	1		T13	6
valid_sources[0x5d]	61944	1			T25	2		T1	1		T11	4
valid_sources[0x5e]	62150	1			T1	8		T11	3		T13	1
valid_sources[0x5f]	76745	1			T24	11		T1	3		T11	3
valid_sources[0x60]	66078	1			T24	14		T1	2		T12	2
valid_sources[0x61]	66462	1			T24	6		T1	7		T11	3
valid_sources[0x62]	67747	1			T24	4		T11	1		T13	5
valid_sources[0x63]	63334	1			T1	4		T11	2		T14	548
valid_sources[0x64]	64130	1			T11	1		T12	1		T13	1
valid_sources[0x65]	65306	1			T1	2		T11	1		T14	580
valid_sources[0x66]	63149	1			T1	1		T13	2		T14	539
valid_sources[0x67]	57604	1			T1	3		T11	1		T13	3
valid_sources[0x68]	59128	1			T1	1		T11	2		T13	4
valid_sources[0x69]	69518	1			T24	3		T1	2		T13	3
valid_sources[0x6a]	59874	1			T24	2		T1	1		T11	1
valid_sources[0x6b]	59164	1			T24	6		T25	3		T1	6
valid_sources[0x6c]	56730	1			T1	7		T11	1		T14	568
valid_sources[0x6d]	60382	1			T24	5		T1	1		T11	3
valid_sources[0x6e]	62663	1			T25	6		T11	1		T2	2
valid_sources[0x6f]	62803	1			T24	3		T14	565		T47	1
valid_sources[0x70]	66407	1			T24	1		T25	3		T1	3
valid_sources[0x71]	65196	1			T24	4		T26	174		T1	2
valid_sources[0x72]	66758	1			T24	1		T25	7		T13	2
valid_sources[0x73]	67608	1			T25	1		T1	7		T11	4
valid_sources[0x74]	66737	1			T1	10		T11	3		T12	1
valid_sources[0x75]	63213	1			T24	1		T25	2		T1	10
valid_sources[0x76]	62556	1			T24	4		T1	1		T11	3
valid_sources[0x77]	63217	1			T1	3		T11	3		T12	1
valid_sources[0x78]	62615	1			T24	2		T1	2		T12	1
valid_sources[0x79]	59533	1			T11	2		T13	1		T14	543
valid_sources[0x7a]	61376	1			T1	2		T11	1		T12	1
valid_sources[0x7b]	64224	1			T24	2		T25	4		T1	10
valid_sources[0x7c]	62916	1			T24	3		T1	2		T11	1
valid_sources[0x7d]	59336	1			T24	2		T1	5		T11	3
valid_sources[0x7e]	64268	1			T24	3		T25	3		T1	1
valid_sources[0x7f]	65543	1			T11	1		T12	2		T13	2
valid_sources[0x80]	61852	1			T1	1		T13	5		T14	542

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3977688

1

T23

1047

T24

41

T25

21

values[0x0]

all_enables

biggest_size

5076363

1

T23

167

T24

203

T25

88

values[0x1]

all_enables

biggest_size

5073670

1

T23

129

T24

181

T25

109