Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	140054137	0	0	0
ctrl_en_input_filter_rd_A	140054137	76317	0	0
intr_ctrl_en_falling_rd_A	140054137	77653	0	0
intr_ctrl_en_lvlhigh_rd_A	140054137	76688	0	0
intr_ctrl_en_lvllow_rd_A	140054137	78859	0	0
intr_ctrl_en_rising_rd_A	140054137	74933	0	0
intr_enable_rd_A	140054137	77684	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140054137	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140054137	76317	0	0
T1	7297	40	0	0
T2	9193	16	0	0
T3	0	23	0	0
T4	0	2335	0	0
T5	0	11	0	0
T6	0	1	0	0
T7	0	220	0	0
T8	0	6541	0	0
T9	0	4973	0	0
T10	0	219	0	0
T11	4284	0	0	0
T12	2366	0	0	0
T13	7102	0	0	0
T14	646129	0	0	0
T15	2611	0	0	0
T16	3657	0	0	0
T17	3986	0	0	0
T18	2911	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140054137	77653	0	0
T1	7297	23	0	0
T2	9193	11	0	0
T3	0	22	0	0
T4	0	2377	0	0
T7	0	184	0	0
T8	0	6702	0	0
T9	0	4698	0	0
T10	0	124	0	0
T11	4284	0	0	0
T12	2366	0	0	0
T13	7102	0	0	0
T14	646129	0	0	0
T15	2611	0	0	0
T16	3657	0	0	0
T17	3986	0	0	0
T18	2911	0	0	0
T19	0	322	0	0
T20	0	4961	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140054137	76688	0	0
T1	7297	29	0	0
T2	9193	0	0	0
T3	0	63	0	0
T4	0	2454	0	0
T7	0	220	0	0
T8	0	6308	0	0
T9	0	5069	0	0
T10	0	165	0	0
T11	4284	0	0	0
T12	2366	0	0	0
T13	7102	0	0	0
T14	646129	0	0	0
T15	2611	0	0	0
T16	3657	0	0	0
T17	3986	0	0	0
T18	2911	0	0	0
T19	0	345	0	0
T20	0	5145	0	0
T21	0	5136	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140054137	78859	0	0
T1	7297	19	0	0
T2	9193	8	0	0
T3	0	33	0	0
T4	0	2360	0	0
T5	0	5	0	0
T7	0	138	0	0
T8	0	6805	0	0
T9	0	4960	0	0
T10	0	202	0	0
T11	4284	0	0	0
T12	2366	0	0	0
T13	7102	0	0	0
T14	646129	0	0	0
T15	2611	0	0	0
T16	3657	0	0	0
T17	3986	0	0	0
T18	2911	0	0	0
T19	0	361	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140054137	74933	0	0
T1	7297	21	0	0
T2	9193	0	0	0
T3	0	29	0	0
T4	0	2442	0	0
T7	0	171	0	0
T8	0	6269	0	0
T9	0	4563	0	0
T10	0	174	0	0
T11	4284	0	0	0
T12	2366	0	0	0
T13	7102	0	0	0
T14	646129	0	0	0
T15	2611	0	0	0
T16	3657	0	0	0
T17	3986	0	0	0
T18	2911	0	0	0
T19	0	313	0	0
T20	0	5073	0	0
T22	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140054137	77684	0	0
T1	7297	41	0	0
T2	9193	4	0	0
T3	0	49	0	0
T4	0	2339	0	0
T7	0	141	0	0
T8	0	6420	0	0
T9	0	5004	0	0
T10	0	203	0	0
T11	4284	0	0	0
T12	2366	0	0	0
T13	7102	0	0	0
T14	646129	0	0	0
T15	2611	0	0	0
T16	3657	0	0	0
T17	3986	0	0	0
T18	2911	0	0	0
T19	0	273	0	0
T22	0	4	0	0