Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3602590	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16064277

1

T22

208

T23

386

T24

276

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7868066	1			T22	46		T23	212		T24	103
values[0x0]	5797656	1			T22	95		T23	138		T24	115
values[0x1]	6001145	1			T22	93		T23	141		T24	99

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2768785	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16898082

1

T22

213

T23

405

T24

285

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	68325	1			T22	1		T25	1		T28	1
valid_sources[0x01]	73019	1			T22	1		T23	5		T29	1
valid_sources[0x02]	66621	1			T23	1		T24	1		T25	1
valid_sources[0x03]	76847	1			T22	1		T24	4		T25	1
valid_sources[0x04]	64412	1			T26	2		T27	2		T29	1
valid_sources[0x05]	72713	1			T23	10		T24	5		T27	1
valid_sources[0x06]	67137	1			T22	3		T24	2		T29	4
valid_sources[0x07]	73872	1			T22	2		T23	7		T25	1
valid_sources[0x08]	73041	1			T24	1		T27	1		T29	2
valid_sources[0x09]	70179	1			T25	1		T27	1		T29	2
valid_sources[0x0a]	67475	1			T24	4		T25	2		T27	2
valid_sources[0x0b]	63896	1			T22	1		T25	1		T27	3
valid_sources[0x0c]	68064	1			T22	1		T25	1		T27	6
valid_sources[0x0d]	71049	1			T22	1		T23	1		T24	2
valid_sources[0x0e]	64275	1			T22	1		T27	3		T29	1
valid_sources[0x0f]	72038	1			T22	2		T23	3		T29	2
valid_sources[0x10]	71535	1			T22	1		T25	1		T27	4
valid_sources[0x11]	61139	1			T22	1		T23	5		T24	3
valid_sources[0x12]	72933	1			T22	1		T1	2		T12	25
valid_sources[0x13]	70824	1			T22	1		T24	2		T27	2
valid_sources[0x14]	77699	1			T22	2		T25	1		T27	2
valid_sources[0x15]	71606	1			T22	3		T27	3		T29	2
valid_sources[0x16]	72128	1			T24	2		T25	1		T29	2
valid_sources[0x17]	71282	1			T22	2		T24	9		T29	1
valid_sources[0x18]	66086	1			T22	1		T24	5		T25	2
valid_sources[0x19]	177504	1			T22	1		T24	2		T25	2
valid_sources[0x1a]	75444	1			T24	2		T27	1		T1	3
valid_sources[0x1b]	80079	1			T22	1		T25	1		T27	2
valid_sources[0x1c]	140448	1			T22	2		T24	1		T27	1
valid_sources[0x1d]	73303	1			T22	1		T23	1		T24	3
valid_sources[0x1e]	67680	1			T22	1		T23	4		T24	2
valid_sources[0x1f]	70409	1			T24	3		T27	4		T28	8
valid_sources[0x20]	68095	1			T22	1		T24	4		T25	1
valid_sources[0x21]	75804	1			T25	1		T27	2		T12	3
valid_sources[0x22]	68102	1			T27	1		T29	2		T1	2
valid_sources[0x23]	108878	1			T23	1		T25	2		T27	1
valid_sources[0x24]	63862	1			T22	3		T27	2		T28	6
valid_sources[0x25]	83906	1			T22	1		T25	1		T27	4
valid_sources[0x26]	69142	1			T22	1		T25	2		T27	3
valid_sources[0x27]	73036	1			T22	1		T25	1		T27	2
valid_sources[0x28]	77115	1			T23	3		T25	1		T27	2
valid_sources[0x29]	75494	1			T22	1		T24	1		T25	1
valid_sources[0x2a]	69765	1			T22	1		T25	1		T27	3
valid_sources[0x2b]	71143	1			T22	1		T24	1		T25	1
valid_sources[0x2c]	62594	1			T25	3		T28	2		T29	2
valid_sources[0x2d]	66886	1			T22	1		T25	1		T27	1
valid_sources[0x2e]	69977	1			T24	3		T25	1		T27	4
valid_sources[0x2f]	82635	1			T22	1		T24	15		T27	1
valid_sources[0x30]	73794	1			T23	2		T24	2		T25	1
valid_sources[0x31]	73879	1			T24	2		T25	2		T29	1
valid_sources[0x32]	78385	1			T22	1		T24	1		T27	2
valid_sources[0x33]	64348	1			T22	2		T25	1		T27	1
valid_sources[0x34]	74478	1			T29	1		T1	2		T12	13
valid_sources[0x35]	72416	1			T26	1		T27	2		T29	1
valid_sources[0x36]	65467	1			T25	3		T27	4		T1	4
valid_sources[0x37]	390785	1			T27	2		T1	2		T12	4
valid_sources[0x38]	73882	1			T22	2		T23	15		T28	4
valid_sources[0x39]	66524	1			T27	2		T29	1		T1	3
valid_sources[0x3a]	71998	1			T22	1		T23	6		T27	1
valid_sources[0x3b]	69023	1			T27	2		T28	1		T29	1
valid_sources[0x3c]	70896	1			T24	2		T29	1		T1	4
valid_sources[0x3d]	71770	1			T24	1		T28	3		T1	2
valid_sources[0x3e]	79495	1			T25	5		T27	2		T28	2
valid_sources[0x3f]	212989	1			T22	1		T25	3		T1	5
valid_sources[0x40]	64069	1			T24	6		T25	1		T27	2
valid_sources[0x41]	68412	1			T25	4		T28	10		T12	3
valid_sources[0x42]	70586	1			T25	1		T27	1		T29	1
valid_sources[0x43]	74981	1			T22	2		T25	1		T27	2
valid_sources[0x44]	65125	1			T22	1		T24	4		T27	1
valid_sources[0x45]	79078	1			T23	8		T25	3		T27	1
valid_sources[0x46]	78790	1			T22	1		T23	10		T25	1
valid_sources[0x47]	75125	1			T23	6		T25	1		T28	2
valid_sources[0x48]	67942	1			T24	1		T25	1		T27	3
valid_sources[0x49]	74754	1			T24	2		T25	1		T29	3
valid_sources[0x4a]	68667	1			T25	1		T27	2		T28	1
valid_sources[0x4b]	75903	1			T22	2		T24	1		T27	2
valid_sources[0x4c]	186810	1			T22	1		T25	6		T27	1
valid_sources[0x4d]	87504	1			T22	1		T25	1		T27	2
valid_sources[0x4e]	67301	1			T28	3		T29	3		T1	3
valid_sources[0x4f]	70012	1			T24	4		T25	1		T27	3
valid_sources[0x50]	69183	1			T24	3		T25	1		T27	2
valid_sources[0x51]	72316	1			T24	2		T27	2		T29	2
valid_sources[0x52]	76079	1			T22	2		T25	1		T27	1
valid_sources[0x53]	78650	1			T22	3		T25	1		T27	3
valid_sources[0x54]	67318	1			T22	1		T24	1		T29	1
valid_sources[0x55]	69382	1			T22	1		T25	1		T29	2
valid_sources[0x56]	72717	1			T22	1		T24	1		T25	1
valid_sources[0x57]	65843	1			T27	5		T28	7		T29	1
valid_sources[0x58]	74091	1			T23	2		T24	2		T27	1
valid_sources[0x59]	66487	1			T22	1		T23	6		T25	2
valid_sources[0x5a]	67576	1			T22	3		T25	1		T27	3
valid_sources[0x5b]	71970	1			T24	6		T27	2		T29	1
valid_sources[0x5c]	70107	1			T22	1		T25	1		T29	1
valid_sources[0x5d]	72102	1			T22	1		T27	2		T28	4
valid_sources[0x5e]	72048	1			T27	2		T28	4		T29	1
valid_sources[0x5f]	62460	1			T22	2		T24	1		T27	2
valid_sources[0x60]	185848	1			T24	1		T25	3		T27	2
valid_sources[0x61]	59548	1			T22	1		T23	2		T1	5
valid_sources[0x62]	73927	1			T22	1		T24	9		T25	3
valid_sources[0x63]	65374	1			T26	1		T27	1		T28	1
valid_sources[0x64]	72511	1			T22	1		T23	5		T25	2
valid_sources[0x65]	73432	1			T22	1		T29	3		T12	13
valid_sources[0x66]	68107	1			T22	3		T24	5		T25	1
valid_sources[0x67]	71890	1			T24	3		T27	2		T29	1
valid_sources[0x68]	72341	1			T22	1		T23	2		T24	2
valid_sources[0x69]	70202	1			T25	1		T27	2		T29	2
valid_sources[0x6a]	72349	1			T24	1		T29	1		T1	5
valid_sources[0x6b]	76251	1			T23	12		T25	1		T27	2
valid_sources[0x6c]	67933	1			T22	1		T25	5		T27	4
valid_sources[0x6d]	68838	1			T22	1		T24	3		T27	1
valid_sources[0x6e]	67590	1			T22	1		T27	2		T1	3
valid_sources[0x6f]	69128	1			T22	1		T23	13		T24	8
valid_sources[0x70]	66302	1			T22	1		T29	2		T1	3
valid_sources[0x71]	67806	1			T22	3		T25	1		T27	4
valid_sources[0x72]	70690	1			T24	4		T25	1		T27	3
valid_sources[0x73]	69825	1			T22	2		T24	5		T1	2
valid_sources[0x74]	65987	1			T22	1		T27	2		T28	1
valid_sources[0x75]	69630	1			T22	1		T24	1		T25	1
valid_sources[0x76]	63908	1			T22	2		T24	8		T28	2
valid_sources[0x77]	74575	1			T22	3		T23	2		T25	1
valid_sources[0x78]	68046	1			T22	2		T23	8		T24	2
valid_sources[0x79]	66561	1			T22	1		T24	2		T26	4
valid_sources[0x7a]	71055	1			T22	1		T25	2		T27	1
valid_sources[0x7b]	71838	1			T1	2		T12	22		T16	1
valid_sources[0x7c]	67288	1			T22	2		T23	3		T24	2
valid_sources[0x7d]	76392	1			T22	1		T25	3		T27	1
valid_sources[0x7e]	70073	1			T22	1		T24	1		T25	4
valid_sources[0x7f]	194096	1			T22	2		T24	3		T25	2
valid_sources[0x80]	69985	1			T24	4		T25	3		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4510130

1

T22

20

T23

107

T24

62

values[0x0]

all_enables

biggest_size

5777146

1

T22

95

T23

138

T24

115

values[0x1]

all_enables

biggest_size

5777001

1

T22

93

T23

141

T24

99