Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	161482657	0	0	0
ctrl_en_input_filter_rd_A	161482657	55275	0	0
intr_ctrl_en_falling_rd_A	161482657	56235	0	0
intr_ctrl_en_lvlhigh_rd_A	161482657	55439	0	0
intr_ctrl_en_lvllow_rd_A	161482657	57491	0	0
intr_ctrl_en_rising_rd_A	161482657	55611	0	0
intr_enable_rd_A	161482657	55782	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161482657	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161482657	55275	0	0
T1	8996	78	0	0
T2	0	3060	0	0
T3	0	6341	0	0
T4	0	266	0	0
T5	0	1149	0	0
T6	0	3881	0	0
T7	0	260	0	0
T8	0	2191	0	0
T9	0	128	0	0
T10	0	2	0	0
T11	1402	0	0	0
T12	8429	0	0	0
T13	551901	0	0	0
T14	2944	0	0	0
T15	13889	0	0	0
T16	2720	0	0	0
T17	4460	0	0	0
T18	3682	0	0	0
T19	8279	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161482657	56235	0	0
T1	8996	73	0	0
T2	0	3114	0	0
T3	0	6892	0	0
T4	0	214	0	0
T5	0	1079	0	0
T6	0	3773	0	0
T7	0	230	0	0
T8	0	2122	0	0
T9	0	101	0	0
T11	1402	0	0	0
T12	8429	0	0	0
T13	551901	0	0	0
T14	2944	0	0	0
T15	13889	0	0	0
T16	2720	0	0	0
T17	4460	0	0	0
T18	3682	0	0	0
T19	8279	0	0	0
T20	0	12	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161482657	55439	0	0
T1	8996	46	0	0
T2	0	3146	0	0
T3	0	6587	0	0
T4	0	268	0	0
T5	0	1095	0	0
T6	0	3857	0	0
T7	0	232	0	0
T8	0	2265	0	0
T9	0	80	0	0
T11	1402	0	0	0
T12	8429	0	0	0
T13	551901	0	0	0
T14	2944	0	0	0
T15	13889	0	0	0
T16	2720	0	0	0
T17	4460	0	0	0
T18	3682	0	0	0
T19	8279	0	0	0
T21	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161482657	57491	0	0
T1	8996	51	0	0
T2	0	3354	0	0
T3	0	7404	0	0
T4	0	284	0	0
T5	0	1096	0	0
T6	0	3930	0	0
T7	0	292	0	0
T8	0	2205	0	0
T9	0	102	0	0
T10	0	11	0	0
T11	1402	0	0	0
T12	8429	0	0	0
T13	551901	0	0	0
T14	2944	0	0	0
T15	13889	0	0	0
T16	2720	0	0	0
T17	4460	0	0	0
T18	3682	0	0	0
T19	8279	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161482657	55611	0	0
T1	8996	96	0	0
T2	0	3244	0	0
T3	0	6502	0	0
T4	0	271	0	0
T5	0	1080	0	0
T6	0	3932	0	0
T7	0	260	0	0
T8	0	2294	0	0
T9	0	94	0	0
T10	0	5	0	0
T11	1402	0	0	0
T12	8429	0	0	0
T13	551901	0	0	0
T14	2944	0	0	0
T15	13889	0	0	0
T16	2720	0	0	0
T17	4460	0	0	0
T18	3682	0	0	0
T19	8279	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161482657	55782	0	0
T1	8996	60	0	0
T2	0	3151	0	0
T3	0	6533	0	0
T4	0	208	0	0
T5	0	1179	0	0
T6	0	3709	0	0
T7	0	202	0	0
T8	0	2301	0	0
T9	0	105	0	0
T10	0	4	0	0
T11	1402	0	0	0
T12	8429	0	0	0
T13	551901	0	0	0
T14	2944	0	0	0
T15	13889	0	0	0
T16	2720	0	0	0
T17	4460	0	0	0
T18	3682	0	0	0
T19	8279	0	0	0