Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	159811913	0	0	0
ctrl_en_input_filter_rd_A	159811913	84509	0	0
intr_ctrl_en_falling_rd_A	159811913	88141	0	0
intr_ctrl_en_lvlhigh_rd_A	159811913	83786	0	0
intr_ctrl_en_lvllow_rd_A	159811913	87940	0	0
intr_ctrl_en_rising_rd_A	159811913	85455	0	0
intr_enable_rd_A	159811913	85655	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159811913	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159811913	84509	0	0
T1	123474	2932	0	0
T2	0	368	0	0
T3	0	238	0	0
T4	0	3954	0	0
T5	0	141	0	0
T6	0	5680	0	0
T7	0	271	0	0
T8	0	3289	0	0
T9	0	2955	0	0
T10	0	5057	0	0
T11	7318	0	0	0
T12	1379	0	0	0
T13	7783	0	0	0
T14	211651	0	0	0
T15	5534	0	0	0
T16	4981	0	0	0
T17	10036	0	0	0
T18	100021	0	0	0
T19	6039	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159811913	88141	0	0
T1	123474	2956	0	0
T2	0	208	0	0
T3	0	203	0	0
T4	0	3771	0	0
T5	0	137	0	0
T6	0	6247	0	0
T7	0	184	0	0
T8	0	3119	0	0
T9	0	2974	0	0
T11	7318	0	0	0
T12	1379	0	0	0
T13	7783	8	0	0
T14	211651	0	0	0
T15	5534	0	0	0
T16	4981	0	0	0
T17	10036	0	0	0
T18	100021	0	0	0
T19	6039	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159811913	83786	0	0
T1	123474	2620	0	0
T2	0	244	0	0
T3	0	160	0	0
T4	0	4078	0	0
T5	0	171	0	0
T6	0	5777	0	0
T7	0	204	0	0
T8	0	3200	0	0
T9	0	2906	0	0
T11	7318	0	0	0
T12	1379	0	0	0
T13	7783	4	0	0
T14	211651	0	0	0
T15	5534	0	0	0
T16	4981	0	0	0
T17	10036	0	0	0
T18	100021	0	0	0
T19	6039	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159811913	87940	0	0
T1	123474	2787	0	0
T2	0	266	0	0
T3	0	155	0	0
T4	0	3842	0	0
T5	0	117	0	0
T6	0	6082	0	0
T7	0	221	0	0
T8	0	3394	0	0
T9	0	2840	0	0
T11	7318	0	0	0
T12	1379	0	0	0
T13	7783	6	0	0
T14	211651	0	0	0
T15	5534	0	0	0
T16	4981	0	0	0
T17	10036	0	0	0
T18	100021	0	0	0
T19	6039	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159811913	85455	0	0
T1	123474	2804	0	0
T2	0	307	0	0
T3	0	168	0	0
T4	0	3916	0	0
T5	0	99	0	0
T6	0	5934	0	0
T7	0	274	0	0
T8	0	3253	0	0
T9	0	2840	0	0
T10	0	5482	0	0
T11	7318	0	0	0
T12	1379	0	0	0
T13	7783	0	0	0
T14	211651	0	0	0
T15	5534	0	0	0
T16	4981	0	0	0
T17	10036	0	0	0
T18	100021	0	0	0
T19	6039	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159811913	85655	0	0
T1	123474	3135	0	0
T2	0	203	0	0
T3	0	188	0	0
T4	0	3791	0	0
T5	0	164	0	0
T6	0	5856	0	0
T7	0	232	0	0
T8	0	3242	0	0
T9	0	2958	0	0
T10	0	5406	0	0
T11	7318	0	0	0
T12	1379	0	0	0
T13	7783	0	0	0
T14	211651	0	0	0
T15	5534	0	0	0
T16	4981	0	0	0
T17	10036	0	0	0
T18	100021	0	0	0
T19	6039	0	0	0