Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2650929	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10937544

1

T21

386

T22

280

T23

185

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5637798	1			T21	486		T22	147		T23	126
values[0x0]	3922811	1			T21	71		T22	93		T23	56
values[0x1]	4027864	1			T21	70		T22	115		T23	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2062111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

11526362

1

T21

443

T22

292

T23

196

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	43332	1			T26	1		T27	412		T28	3
valid_sources[0x01]	47522	1			T26	2		T27	421		T28	2
valid_sources[0x02]	50365	1			T23	1		T26	4		T27	371
valid_sources[0x03]	46173	1			T23	1		T25	7		T27	432
valid_sources[0x04]	48269	1			T23	2		T25	2		T26	2
valid_sources[0x05]	47110	1			T25	5		T26	2		T27	343
valid_sources[0x06]	51609	1			T23	6		T26	1		T27	377
valid_sources[0x07]	45963	1			T25	3		T26	1		T27	444
valid_sources[0x08]	50475	1			T23	4		T25	1		T26	4
valid_sources[0x09]	51727	1			T26	1		T27	474		T28	4
valid_sources[0x0a]	54541	1			T26	2		T27	426		T28	4
valid_sources[0x0b]	50970	1			T25	1		T26	1		T27	393
valid_sources[0x0c]	43158	1			T26	3		T27	385		T29	5
valid_sources[0x0d]	156914	1			T25	1		T26	2		T27	402
valid_sources[0x0e]	52586	1			T23	3		T26	1		T27	411
valid_sources[0x0f]	51605	1			T25	2		T26	2		T27	461
valid_sources[0x10]	44539	1			T25	5		T26	3		T27	390
valid_sources[0x11]	44539	1			T23	2		T25	5		T26	3
valid_sources[0x12]	48895	1			T23	9		T26	1		T27	455
valid_sources[0x13]	50906	1			T26	2		T27	513		T29	4
valid_sources[0x14]	51345	1			T23	1		T25	3		T26	1
valid_sources[0x15]	48363	1			T25	4		T26	1		T27	471
valid_sources[0x16]	44026	1			T23	3		T25	1		T26	1
valid_sources[0x17]	46069	1			T23	1		T25	1		T26	2
valid_sources[0x18]	45653	1			T25	2		T27	425		T28	1
valid_sources[0x19]	45931	1			T25	2		T26	1		T27	447
valid_sources[0x1a]	51232	1			T26	2		T27	425		T29	3
valid_sources[0x1b]	45369	1			T25	1		T27	394		T28	3
valid_sources[0x1c]	47498	1			T25	2		T27	434		T29	4
valid_sources[0x1d]	44065	1			T25	2		T26	1		T27	441
valid_sources[0x1e]	45215	1			T25	1		T26	1		T27	468
valid_sources[0x1f]	47043	1			T25	7		T26	2		T27	439
valid_sources[0x20]	47280	1			T25	5		T26	2		T27	436
valid_sources[0x21]	48099	1			T23	2		T26	5		T27	355
valid_sources[0x22]	50665	1			T23	1		T25	2		T26	1
valid_sources[0x23]	42674	1			T26	1		T27	485		T29	3
valid_sources[0x24]	53674	1			T25	4		T26	2		T27	407
valid_sources[0x25]	104691	1			T25	1		T26	1		T27	414
valid_sources[0x26]	49139	1			T25	2		T26	4		T27	423
valid_sources[0x27]	44146	1			T23	1		T25	3		T26	1
valid_sources[0x28]	47464	1			T25	4		T26	1		T27	374
valid_sources[0x29]	48501	1			T25	1		T26	2		T27	432
valid_sources[0x2a]	44663	1			T23	8		T25	1		T26	1
valid_sources[0x2b]	49800	1			T26	4		T27	403		T29	2
valid_sources[0x2c]	49728	1			T23	3		T27	379		T29	5
valid_sources[0x2d]	53618	1			T23	1		T25	3		T26	3
valid_sources[0x2e]	49146	1			T25	1		T26	3		T27	362
valid_sources[0x2f]	47545	1			T26	2		T27	415		T29	1
valid_sources[0x30]	96573	1			T27	473		T28	1		T29	3
valid_sources[0x31]	47782	1			T25	12		T27	405		T28	2
valid_sources[0x32]	46092	1			T26	2		T27	407		T29	3
valid_sources[0x33]	43207	1			T25	4		T26	4		T27	487
valid_sources[0x34]	45277	1			T26	3		T27	410		T28	1
valid_sources[0x35]	44215	1			T26	2		T27	369		T29	12
valid_sources[0x36]	43536	1			T25	1		T26	4		T27	410
valid_sources[0x37]	47641	1			T25	4		T27	406		T29	2
valid_sources[0x38]	45843	1			T26	4		T27	464		T121	6
valid_sources[0x39]	47593	1			T23	1		T26	2		T27	366
valid_sources[0x3a]	46256	1			T23	4		T25	1		T27	398
valid_sources[0x3b]	46233	1			T26	3		T27	476		T28	1
valid_sources[0x3c]	47886	1			T23	2		T25	3		T26	3
valid_sources[0x3d]	48557	1			T23	4		T27	487		T28	1
valid_sources[0x3e]	44794	1			T26	1		T27	392		T28	1
valid_sources[0x3f]	49200	1			T25	2		T26	2		T27	414
valid_sources[0x40]	50851	1			T26	3		T27	430		T29	3
valid_sources[0x41]	47152	1			T23	1		T25	1		T26	5
valid_sources[0x42]	43052	1			T25	1		T26	3		T27	334
valid_sources[0x43]	42628	1			T23	3		T26	2		T27	429
valid_sources[0x44]	152187	1			T26	2		T27	454		T29	2
valid_sources[0x45]	48836	1			T27	418		T28	1		T29	6
valid_sources[0x46]	109297	1			T25	4		T26	1		T27	404
valid_sources[0x47]	82145	1			T25	1		T26	1		T27	421
valid_sources[0x48]	50838	1			T26	1		T27	381		T28	1
valid_sources[0x49]	45800	1			T27	424		T29	1		T121	9
valid_sources[0x4a]	50879	1			T23	2		T25	1		T27	392
valid_sources[0x4b]	48469	1			T23	2		T25	7		T27	437
valid_sources[0x4c]	48297	1			T23	1		T26	5		T27	391
valid_sources[0x4d]	45751	1			T25	4		T26	4		T27	361
valid_sources[0x4e]	44495	1			T26	2		T27	454		T29	6
valid_sources[0x4f]	47779	1			T23	2		T26	1		T27	347
valid_sources[0x50]	44354	1			T26	1		T27	400		T28	2
valid_sources[0x51]	48717	1			T26	4		T27	440		T29	7
valid_sources[0x52]	46464	1			T22	355		T23	6		T25	3
valid_sources[0x53]	44190	1			T25	4		T26	2		T27	353
valid_sources[0x54]	55598	1			T23	1		T26	1		T27	451
valid_sources[0x55]	141843	1			T26	3		T27	388		T28	1
valid_sources[0x56]	47331	1			T26	1		T27	430		T28	1
valid_sources[0x57]	45739	1			T23	9		T25	2		T26	1
valid_sources[0x58]	47698	1			T23	5		T25	1		T27	402
valid_sources[0x59]	43103	1			T23	1		T25	3		T26	1
valid_sources[0x5a]	43771	1			T23	3		T25	2		T27	421
valid_sources[0x5b]	80789	1			T25	1		T26	1		T27	368
valid_sources[0x5c]	48468	1			T25	6		T26	1		T27	484
valid_sources[0x5d]	45035	1			T25	5		T26	1		T27	403
valid_sources[0x5e]	44602	1			T26	1		T27	458		T28	3
valid_sources[0x5f]	45188	1			T23	1		T26	1		T27	471
valid_sources[0x60]	45338	1			T25	3		T26	3		T27	452
valid_sources[0x61]	45184	1			T25	1		T26	2		T27	450
valid_sources[0x62]	48521	1			T23	2		T26	1		T27	373
valid_sources[0x63]	49132	1			T27	419		T28	1		T29	5
valid_sources[0x64]	47312	1			T23	1		T25	6		T26	1
valid_sources[0x65]	62274	1			T25	1		T26	2		T27	468
valid_sources[0x66]	45010	1			T26	3		T27	375		T29	6
valid_sources[0x67]	46743	1			T25	2		T26	2		T27	430
valid_sources[0x68]	48552	1			T27	396		T28	1		T29	2
valid_sources[0x69]	45681	1			T25	3		T26	2		T27	422
valid_sources[0x6a]	47316	1			T25	2		T26	1		T27	428
valid_sources[0x6b]	47664	1			T25	1		T26	4		T27	401
valid_sources[0x6c]	48830	1			T27	421		T29	5		T121	4
valid_sources[0x6d]	49312	1			T25	2		T26	3		T27	479
valid_sources[0x6e]	42691	1			T23	5		T26	4		T27	320
valid_sources[0x6f]	45549	1			T26	1		T27	301		T28	1
valid_sources[0x70]	48271	1			T23	2		T25	1		T27	469
valid_sources[0x71]	75991	1			T25	3		T26	2		T27	433
valid_sources[0x72]	245625	1			T25	1		T27	448		T29	3
valid_sources[0x73]	46771	1			T26	1		T27	475		T28	2
valid_sources[0x74]	45682	1			T26	2		T27	469		T28	1
valid_sources[0x75]	46951	1			T23	2		T26	1		T27	457
valid_sources[0x76]	44755	1			T25	1		T26	1		T27	399
valid_sources[0x77]	46222	1			T23	3		T25	7		T27	438
valid_sources[0x78]	49434	1			T26	3		T27	427		T29	3
valid_sources[0x79]	53210	1			T23	1		T27	427		T29	3
valid_sources[0x7a]	44507	1			T23	1		T25	1		T26	1
valid_sources[0x7b]	44685	1			T26	1		T27	407		T28	2
valid_sources[0x7c]	43830	1			T25	4		T26	2		T27	429
valid_sources[0x7d]	48710	1			T25	3		T26	3		T27	422
valid_sources[0x7e]	48462	1			T25	1		T26	6		T27	351
valid_sources[0x7f]	47577	1			T26	4		T27	403		T29	3
valid_sources[0x80]	44031	1			T25	2		T26	1		T27	376

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3110466

1

T21

245

T22

72

T23

73

values[0x0]

all_enables

biggest_size

3912388

1

T21

71

T22

93

T23

56

values[0x1]

all_enables

biggest_size

3914690

1

T21

70

T22

115

T23

56