Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105327017	0	0	0
ctrl_en_input_filter_rd_A	105327017	64040	0	0
intr_ctrl_en_falling_rd_A	105327017	64041	0	0
intr_ctrl_en_lvlhigh_rd_A	105327017	65716	0	0
intr_ctrl_en_lvllow_rd_A	105327017	63829	0	0
intr_ctrl_en_rising_rd_A	105327017	64244	0	0
intr_enable_rd_A	105327017	63970	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105327017	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105327017	64040	0	0
T1	25166	184	0	0
T2	544060	1211	0	0
T3	0	6	0	0
T4	0	302	0	0
T5	0	9	0	0
T6	0	5673	0	0
T7	0	1607	0	0
T8	0	80	0	0
T9	0	5929	0	0
T10	0	634	0	0
T11	5927	0	0	0
T12	2836	0	0	0
T13	7958	0	0	0
T14	4872	0	0	0
T15	1480	0	0	0
T16	3925	0	0	0
T17	6194	0	0	0
T18	1882	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105327017	64041	0	0
T1	25166	214	0	0
T2	544060	1199	0	0
T4	0	288	0	0
T6	0	5492	0	0
T7	0	1798	0	0
T8	0	133	0	0
T9	0	6269	0	0
T10	0	658	0	0
T11	5927	0	0	0
T12	2836	0	0	0
T13	7958	0	0	0
T14	4872	0	0	0
T15	1480	0	0	0
T16	3925	0	0	0
T17	6194	0	0	0
T18	1882	0	0	0
T19	0	188	0	0
T20	0	5	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105327017	65716	0	0
T1	25166	148	0	0
T2	544060	1301	0	0
T4	0	292	0	0
T5	0	1	0	0
T6	0	5676	0	0
T7	0	1811	0	0
T8	0	148	0	0
T9	0	6113	0	0
T10	0	666	0	0
T11	5927	0	0	0
T12	2836	0	0	0
T13	7958	0	0	0
T14	4872	0	0	0
T15	1480	0	0	0
T16	3925	0	0	0
T17	6194	0	0	0
T18	1882	0	0	0
T19	0	188	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105327017	63829	0	0
T1	25166	191	0	0
T2	544060	1295	0	0
T4	0	283	0	0
T5	0	4	0	0
T6	0	5537	0	0
T7	0	1703	0	0
T8	0	127	0	0
T9	0	5918	0	0
T10	0	541	0	0
T11	5927	0	0	0
T12	2836	0	0	0
T13	7958	0	0	0
T14	4872	0	0	0
T15	1480	0	0	0
T16	3925	0	0	0
T17	6194	0	0	0
T18	1882	0	0	0
T19	0	200	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105327017	64244	0	0
T1	25166	190	0	0
T2	544060	1356	0	0
T4	0	276	0	0
T5	0	3	0	0
T6	0	5540	0	0
T7	0	1727	0	0
T8	0	146	0	0
T9	0	6203	0	0
T10	0	652	0	0
T11	5927	0	0	0
T12	2836	0	0	0
T13	7958	0	0	0
T14	4872	0	0	0
T15	1480	0	0	0
T16	3925	0	0	0
T17	6194	0	0	0
T18	1882	0	0	0
T19	0	209	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105327017	63970	0	0
T1	25166	144	0	0
T2	544060	1369	0	0
T3	0	5	0	0
T4	0	294	0	0
T6	0	5504	0	0
T7	0	1497	0	0
T8	0	124	0	0
T9	0	5979	0	0
T10	0	592	0	0
T11	5927	0	0	0
T12	2836	0	0	0
T13	7958	0	0	0
T14	4872	0	0	0
T15	1480	0	0	0
T16	3925	0	0	0
T17	6194	0	0	0
T18	1882	0	0	0
T19	0	194	0	0