Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3209646	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14597538

1

T22

164

T23

60447

T24

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7067341	1			T21	1		T22	75		T23	33312
values[0x0]	5275292	1			T22	66		T23	21897		T24	8
values[0x1]	5464551	1			T22	61		T23	21898		T24	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2458362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15348822

1

T22

170

T23

63791

T24

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	73977	1			T1	382		T12	1		T2	243
valid_sources[0x01]	67080	1			T22	4		T1	374		T12	2
valid_sources[0x02]	63334	1			T22	2		T1	402		T11	1
valid_sources[0x03]	69982	1			T1	380		T11	4		T12	2
valid_sources[0x04]	62578	1			T22	2		T1	361		T11	1
valid_sources[0x05]	71231	1			T1	429		T11	5		T12	1
valid_sources[0x06]	61580	1			T22	3		T1	377		T2	252
valid_sources[0x07]	67481	1			T1	404		T11	1		T12	1
valid_sources[0x08]	69207	1			T1	388		T11	1		T12	2
valid_sources[0x09]	71758	1			T22	2		T1	399		T11	3
valid_sources[0x0a]	63910	1			T22	6		T1	403		T11	2
valid_sources[0x0b]	72959	1			T22	15		T1	364		T11	2
valid_sources[0x0c]	69723	1			T24	1		T1	370		T2	217
valid_sources[0x0d]	65709	1			T1	376		T12	2		T2	250
valid_sources[0x0e]	73507	1			T1	418		T11	1		T2	266
valid_sources[0x0f]	66714	1			T1	376		T11	1		T12	3
valid_sources[0x10]	64929	1			T1	365		T11	2		T12	1
valid_sources[0x11]	66630	1			T1	380		T11	1		T12	1
valid_sources[0x12]	67115	1			T22	8		T1	364		T12	2
valid_sources[0x13]	64273	1			T1	401		T12	2		T2	246
valid_sources[0x14]	62046	1			T1	392		T12	1		T2	251
valid_sources[0x15]	64925	1			T22	1		T1	426		T12	2
valid_sources[0x16]	64904	1			T22	1		T1	376		T11	1
valid_sources[0x17]	73020	1			T1	390		T12	1		T2	219
valid_sources[0x18]	63433	1			T1	398		T12	1		T2	260
valid_sources[0x19]	61569	1			T1	398		T11	2		T12	2
valid_sources[0x1a]	63631	1			T1	395		T12	1		T2	234
valid_sources[0x1b]	62018	1			T1	416		T2	241		T14	2
valid_sources[0x1c]	66584	1			T1	374		T11	1		T12	3
valid_sources[0x1d]	69267	1			T1	410		T11	2		T12	1
valid_sources[0x1e]	70963	1			T1	390		T2	222		T15	1
valid_sources[0x1f]	64865	1			T1	397		T12	1		T2	214
valid_sources[0x20]	65796	1			T1	392		T12	2		T2	235
valid_sources[0x21]	66682	1			T1	380		T11	2		T12	2
valid_sources[0x22]	63532	1			T1	402		T2	249		T14	1
valid_sources[0x23]	61110	1			T1	379		T11	2		T12	3
valid_sources[0x24]	60797	1			T1	385		T11	2		T12	2
valid_sources[0x25]	62750	1			T1	404		T12	1		T2	229
valid_sources[0x26]	71781	1			T1	408		T11	2		T2	248
valid_sources[0x27]	74967	1			T1	380		T12	1		T2	214
valid_sources[0x28]	73138	1			T22	3		T1	366		T11	2
valid_sources[0x29]	60695	1			T1	391		T11	1		T12	3
valid_sources[0x2a]	70395	1			T1	405		T2	246		T15	3
valid_sources[0x2b]	67704	1			T22	2		T1	409		T11	1
valid_sources[0x2c]	67271	1			T1	412		T12	2		T2	258
valid_sources[0x2d]	63410	1			T1	363		T11	1		T2	234
valid_sources[0x2e]	65230	1			T22	2		T1	378		T11	2
valid_sources[0x2f]	65384	1			T1	393		T2	250		T14	1
valid_sources[0x30]	68994	1			T1	383		T11	2		T12	1
valid_sources[0x31]	66890	1			T1	381		T11	1		T12	1
valid_sources[0x32]	65083	1			T24	2		T1	398		T12	2
valid_sources[0x33]	153965	1			T23	77107		T1	377		T2	271
valid_sources[0x34]	66797	1			T21	1		T1	380		T12	1
valid_sources[0x35]	65778	1			T1	361		T12	2		T2	214
valid_sources[0x36]	69439	1			T1	418		T11	5		T12	2
valid_sources[0x37]	63754	1			T1	376		T11	1		T2	223
valid_sources[0x38]	64148	1			T24	7		T1	381		T2	255
valid_sources[0x39]	62989	1			T1	418		T11	1		T12	1
valid_sources[0x3a]	71938	1			T1	411		T11	2		T2	243
valid_sources[0x3b]	68063	1			T1	423		T2	243		T15	4
valid_sources[0x3c]	65668	1			T22	8		T1	408		T11	2
valid_sources[0x3d]	63207	1			T22	4		T1	390		T2	263
valid_sources[0x3e]	73515	1			T1	400		T11	1		T2	243
valid_sources[0x3f]	67569	1			T1	387		T12	1		T2	225
valid_sources[0x40]	67784	1			T1	404		T12	1		T2	268
valid_sources[0x41]	65833	1			T1	403		T11	1		T12	1
valid_sources[0x42]	70991	1			T1	380		T12	1		T2	245
valid_sources[0x43]	63937	1			T1	369		T12	1		T2	224
valid_sources[0x44]	59601	1			T1	394		T12	2		T2	258
valid_sources[0x45]	67759	1			T1	393		T11	1		T12	3
valid_sources[0x46]	66160	1			T22	3		T1	373		T11	3
valid_sources[0x47]	65414	1			T22	3		T1	406		T12	2
valid_sources[0x48]	67925	1			T1	382		T11	4		T2	248
valid_sources[0x49]	64504	1			T1	408		T12	3		T2	228
valid_sources[0x4a]	69371	1			T1	375		T11	2		T2	232
valid_sources[0x4b]	65782	1			T22	5		T1	431		T11	3
valid_sources[0x4c]	64018	1			T1	388		T2	241		T14	2
valid_sources[0x4d]	72933	1			T1	397		T11	2		T12	2
valid_sources[0x4e]	92739	1			T22	5		T1	396		T11	3
valid_sources[0x4f]	66179	1			T24	5		T1	362		T12	2
valid_sources[0x50]	66699	1			T1	380		T12	1		T2	210
valid_sources[0x51]	66273	1			T1	380		T11	1		T12	3
valid_sources[0x52]	67797	1			T1	377		T11	4		T2	230
valid_sources[0x53]	70934	1			T22	2		T1	396		T2	283
valid_sources[0x54]	65784	1			T1	386		T12	2		T2	225
valid_sources[0x55]	65587	1			T1	412		T12	2		T2	199
valid_sources[0x56]	65515	1			T22	7		T1	410		T12	1
valid_sources[0x57]	65648	1			T1	396		T11	1		T12	1
valid_sources[0x58]	63157	1			T1	399		T11	4		T12	3
valid_sources[0x59]	64883	1			T22	2		T1	404		T12	1
valid_sources[0x5a]	66670	1			T1	366		T2	225		T17	2
valid_sources[0x5b]	72248	1			T1	403		T11	1		T2	238
valid_sources[0x5c]	69063	1			T22	7		T1	353		T12	2
valid_sources[0x5d]	68532	1			T1	389		T11	1		T12	1
valid_sources[0x5e]	70801	1			T1	404		T11	1		T2	252
valid_sources[0x5f]	69062	1			T22	9		T1	373		T12	2
valid_sources[0x60]	66154	1			T1	368		T11	1		T2	258
valid_sources[0x61]	60894	1			T1	379		T11	4		T2	250
valid_sources[0x62]	66672	1			T1	364		T11	1		T12	1
valid_sources[0x63]	62559	1			T1	393		T2	266		T14	1
valid_sources[0x64]	71732	1			T1	377		T11	1		T12	1
valid_sources[0x65]	71979	1			T1	374		T11	1		T12	1
valid_sources[0x66]	63619	1			T1	410		T11	1		T12	1
valid_sources[0x67]	63301	1			T1	393		T12	2		T2	237
valid_sources[0x68]	71981	1			T1	385		T11	1		T12	1
valid_sources[0x69]	103973	1			T22	3		T1	403		T12	1
valid_sources[0x6a]	72738	1			T1	382		T11	1		T2	223
valid_sources[0x6b]	69633	1			T1	386		T11	4		T12	2
valid_sources[0x6c]	69449	1			T1	391		T12	1		T2	218
valid_sources[0x6d]	60987	1			T1	405		T12	1		T2	268
valid_sources[0x6e]	65891	1			T1	367		T11	1		T12	1
valid_sources[0x6f]	69442	1			T1	382		T11	5		T12	1
valid_sources[0x70]	68739	1			T1	393		T11	1		T2	232
valid_sources[0x71]	166961	1			T1	383		T12	2		T2	256
valid_sources[0x72]	61349	1			T1	387		T11	1		T2	248
valid_sources[0x73]	69325	1			T1	392		T11	2		T2	255
valid_sources[0x74]	64729	1			T1	393		T11	1		T2	243
valid_sources[0x75]	64156	1			T1	380		T12	2		T2	225
valid_sources[0x76]	62941	1			T1	393		T12	2		T2	251
valid_sources[0x77]	134401	1			T22	2		T1	398		T11	2
valid_sources[0x78]	73535	1			T1	385		T11	1		T12	3
valid_sources[0x79]	66349	1			T1	372		T12	1		T2	211
valid_sources[0x7a]	71583	1			T1	412		T2	242		T14	2
valid_sources[0x7b]	65476	1			T1	381		T12	1		T2	279
valid_sources[0x7c]	69560	1			T1	411		T11	2		T12	1
valid_sources[0x7d]	71443	1			T1	390		T11	1		T2	262
valid_sources[0x7e]	73481	1			T1	423		T11	1		T12	2
valid_sources[0x7f]	60578	1			T1	398		T12	3		T2	248
valid_sources[0x80]	69251	1			T1	445		T11	2		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4093161

1

T22

37

T23

16652

T24

1

values[0x0]

all_enables

biggest_size

5255318

1

T22

66

T23

21897

T24

1

values[0x1]

all_enables

biggest_size

5249059

1

T22

61

T23

21898

T24

1