Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	159658130	0	0	0
ctrl_en_input_filter_rd_A	159658130	95706	0	0
intr_ctrl_en_falling_rd_A	159658130	99998	0	0
intr_ctrl_en_lvlhigh_rd_A	159658130	94271	0	0
intr_ctrl_en_lvllow_rd_A	159658130	98822	0	0
intr_ctrl_en_rising_rd_A	159658130	95529	0	0
intr_enable_rd_A	159658130	97145	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159658130	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159658130	95706	0	0
T1	132448	4512	0	0
T2	798657	2861	0	0
T3	0	215	0	0
T4	0	366	0	0
T5	0	206	0	0
T6	0	112	0	0
T7	0	282	0	0
T8	0	1152	0	0
T9	0	18672	0	0
T10	0	10	0	0
T11	4582	0	0	0
T12	4298	0	0	0
T13	685870	0	0	0
T14	2678	0	0	0
T15	5153	0	0	0
T16	2577	0	0	0
T17	8593	0	0	0
T18	4842	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159658130	99998	0	0
T1	132448	4365	0	0
T2	798657	3080	0	0
T3	0	183	0	0
T4	0	248	0	0
T5	0	213	0	0
T6	0	69	0	0
T7	0	222	0	0
T8	0	1274	0	0
T9	0	20601	0	0
T11	4582	0	0	0
T12	4298	0	0	0
T13	685870	0	0	0
T14	2678	0	0	0
T15	5153	0	0	0
T16	2577	0	0	0
T17	8593	0	0	0
T18	4842	0	0	0
T19	0	70	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159658130	94271	0	0
T1	132448	4002	0	0
T2	798657	3135	0	0
T3	0	238	0	0
T4	0	222	0	0
T5	0	236	0	0
T6	0	100	0	0
T7	0	253	0	0
T8	0	1269	0	0
T9	0	18600	0	0
T11	4582	0	0	0
T12	4298	0	0	0
T13	685870	0	0	0
T14	2678	0	0	0
T15	5153	0	0	0
T16	2577	0	0	0
T17	8593	0	0	0
T18	4842	0	0	0
T19	0	93	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159658130	98822	0	0
T1	132448	4271	0	0
T2	798657	2874	0	0
T3	0	223	0	0
T4	0	322	0	0
T5	0	312	0	0
T6	0	84	0	0
T7	0	235	0	0
T8	0	1254	0	0
T9	0	20468	0	0
T11	4582	0	0	0
T12	4298	0	0	0
T13	685870	0	0	0
T14	2678	0	0	0
T15	5153	0	0	0
T16	2577	0	0	0
T17	8593	0	0	0
T18	4842	0	0	0
T20	0	2	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159658130	95529	0	0
T1	132448	4629	0	0
T2	798657	3030	0	0
T3	0	328	0	0
T4	0	252	0	0
T5	0	279	0	0
T6	0	91	0	0
T7	0	219	0	0
T8	0	1211	0	0
T9	0	18897	0	0
T11	4582	0	0	0
T12	4298	0	0	0
T13	685870	0	0	0
T14	2678	0	0	0
T15	5153	0	0	0
T16	2577	0	0	0
T17	8593	0	0	0
T18	4842	0	0	0
T19	0	112	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159658130	97145	0	0
T1	132448	4333	0	0
T2	798657	3171	0	0
T3	0	230	0	0
T4	0	319	0	0
T5	0	211	0	0
T6	0	92	0	0
T7	0	211	0	0
T8	0	1233	0	0
T9	0	19921	0	0
T11	4582	0	0	0
T12	4298	0	0	0
T13	685870	0	0	0
T14	2678	0	0	0
T15	5153	0	0	0
T16	2577	0	0	0
T17	8593	0	0	0
T18	4842	0	0	0
T19	0	78	0	0