Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2796634	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12673806

1

T21

243

T22

3

T23

1489

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6143319	1			T21	29		T22	1		T23	1728
values[0x0]	4581821	1			T21	111		T22	1		T23	302
values[0x1]	4745300	1			T21	112		T22	5		T23	310

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2145244	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13325196

1

T21

245

T22

3

T23

1669

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56534	1			T23	1		T24	10		T26	15
valid_sources[0x01]	54201	1			T23	7		T24	5		T26	14
valid_sources[0x02]	54091	1			T23	6		T24	9		T26	17
valid_sources[0x03]	51907	1			T23	5		T24	10		T25	8
valid_sources[0x04]	56991	1			T23	14		T24	11		T25	2
valid_sources[0x05]	52447	1			T21	5		T23	3		T24	11
valid_sources[0x06]	58693	1			T23	5		T24	10		T26	20
valid_sources[0x07]	51720	1			T23	21		T24	11		T26	17
valid_sources[0x08]	52892	1			T23	13		T24	9		T26	7
valid_sources[0x09]	51692	1			T23	14		T24	14		T26	23
valid_sources[0x0a]	55683	1			T23	13		T24	7		T26	10
valid_sources[0x0b]	53191	1			T23	11		T24	9		T25	7
valid_sources[0x0c]	53799	1			T23	8		T24	6		T25	10
valid_sources[0x0d]	54481	1			T23	13		T24	6		T26	10
valid_sources[0x0e]	52139	1			T23	19		T24	12		T26	19
valid_sources[0x0f]	54929	1			T23	11		T24	12		T25	5
valid_sources[0x10]	56747	1			T21	11		T23	13		T24	14
valid_sources[0x11]	55336	1			T23	9		T24	9		T26	6
valid_sources[0x12]	55750	1			T23	7		T24	10		T25	5
valid_sources[0x13]	55407	1			T23	7		T24	6		T26	9
valid_sources[0x14]	56102	1			T23	22		T24	11		T26	14
valid_sources[0x15]	54695	1			T23	9		T24	10		T25	13
valid_sources[0x16]	56122	1			T23	19		T24	11		T25	4
valid_sources[0x17]	53588	1			T23	14		T24	4		T26	9
valid_sources[0x18]	60256	1			T21	8		T23	8		T24	13
valid_sources[0x19]	57538	1			T23	12		T24	12		T26	14
valid_sources[0x1a]	56346	1			T23	11		T24	10		T26	5
valid_sources[0x1b]	56045	1			T21	2		T23	12		T24	7
valid_sources[0x1c]	55436	1			T21	5		T23	5		T24	6
valid_sources[0x1d]	53303	1			T23	6		T24	8		T25	7
valid_sources[0x1e]	55275	1			T23	8		T24	10		T26	6
valid_sources[0x1f]	55200	1			T23	5		T24	15		T26	14
valid_sources[0x20]	50898	1			T23	27		T24	12		T26	8
valid_sources[0x21]	53147	1			T23	16		T24	5		T26	16
valid_sources[0x22]	56126	1			T23	6		T24	14		T25	10
valid_sources[0x23]	57252	1			T21	1		T23	6		T24	6
valid_sources[0x24]	56691	1			T21	10		T23	16		T24	9
valid_sources[0x25]	56925	1			T21	4		T23	8		T24	11
valid_sources[0x26]	54189	1			T23	14		T24	6		T26	15
valid_sources[0x27]	51946	1			T23	26		T24	9		T25	2
valid_sources[0x28]	50707	1			T23	10		T24	21		T25	1
valid_sources[0x29]	53323	1			T23	17		T24	11		T26	7
valid_sources[0x2a]	56223	1			T23	7		T24	7		T26	15
valid_sources[0x2b]	57456	1			T23	7		T24	7		T25	4
valid_sources[0x2c]	54150	1			T23	20		T24	11		T26	11
valid_sources[0x2d]	54055	1			T23	10		T24	13		T26	13
valid_sources[0x2e]	142168	1			T23	3		T24	9		T25	1
valid_sources[0x2f]	53831	1			T23	13		T24	9		T25	6
valid_sources[0x30]	58503	1			T23	13		T24	9		T25	1
valid_sources[0x31]	57150	1			T21	8		T23	4		T24	5
valid_sources[0x32]	51662	1			T23	2		T24	8		T26	15
valid_sources[0x33]	56566	1			T21	2		T23	5		T24	9
valid_sources[0x34]	55088	1			T23	7		T24	7		T25	4
valid_sources[0x35]	56991	1			T23	17		T24	16		T26	10
valid_sources[0x36]	127320	1			T23	7		T24	6		T25	13
valid_sources[0x37]	51052	1			T23	6		T24	5		T26	14
valid_sources[0x38]	51928	1			T23	8		T24	7		T25	1
valid_sources[0x39]	56179	1			T23	11		T24	11		T26	12
valid_sources[0x3a]	52611	1			T22	5		T23	5		T24	13
valid_sources[0x3b]	123416	1			T23	10		T24	10		T26	11
valid_sources[0x3c]	52773	1			T23	9		T24	11		T26	8
valid_sources[0x3d]	52361	1			T23	12		T24	13		T25	8
valid_sources[0x3e]	53580	1			T23	6		T24	6		T26	9
valid_sources[0x3f]	54528	1			T21	10		T23	4		T24	10
valid_sources[0x40]	54443	1			T23	11		T24	6		T26	13
valid_sources[0x41]	53251	1			T23	8		T24	8		T25	2
valid_sources[0x42]	54948	1			T23	3		T24	12		T26	24
valid_sources[0x43]	54087	1			T23	12		T24	9		T26	9
valid_sources[0x44]	52360	1			T23	9		T24	10		T26	15
valid_sources[0x45]	55461	1			T23	5		T24	9		T25	6
valid_sources[0x46]	56581	1			T23	11		T24	6		T26	10
valid_sources[0x47]	51044	1			T21	1		T23	7		T24	9
valid_sources[0x48]	147581	1			T21	1		T23	7		T24	10
valid_sources[0x49]	51099	1			T23	8		T24	15		T26	15
valid_sources[0x4a]	52005	1			T23	5		T24	8		T26	21
valid_sources[0x4b]	57020	1			T23	7		T24	12		T26	10
valid_sources[0x4c]	52503	1			T23	20		T24	9		T26	11
valid_sources[0x4d]	59642	1			T23	4		T24	14		T25	1
valid_sources[0x4e]	171933	1			T23	10		T24	10		T25	4
valid_sources[0x4f]	56945	1			T23	5		T24	10		T26	4
valid_sources[0x50]	56873	1			T23	1		T24	11		T26	2
valid_sources[0x51]	57535	1			T23	4		T24	9		T25	4
valid_sources[0x52]	55691	1			T23	5		T24	5		T25	2
valid_sources[0x53]	50282	1			T23	18		T24	8		T26	23
valid_sources[0x54]	56921	1			T23	12		T24	16		T26	4
valid_sources[0x55]	52529	1			T23	6		T24	17		T26	10
valid_sources[0x56]	57501	1			T23	9		T24	9		T26	5
valid_sources[0x57]	56311	1			T21	2		T23	5		T24	3
valid_sources[0x58]	52559	1			T23	10		T24	7		T25	7
valid_sources[0x59]	131058	1			T23	3		T24	3		T26	13
valid_sources[0x5a]	53047	1			T23	14		T24	7		T26	22
valid_sources[0x5b]	60728	1			T23	17		T24	4		T26	11
valid_sources[0x5c]	53153	1			T23	24		T24	14		T25	6
valid_sources[0x5d]	51674	1			T23	9		T24	10		T26	14
valid_sources[0x5e]	58301	1			T23	12		T24	16		T25	4
valid_sources[0x5f]	54479	1			T23	16		T24	6		T25	12
valid_sources[0x60]	56271	1			T23	4		T24	8		T26	17
valid_sources[0x61]	56543	1			T23	13		T24	15		T26	7
valid_sources[0x62]	56287	1			T21	9		T23	14		T24	10
valid_sources[0x63]	57851	1			T21	5		T23	4		T24	12
valid_sources[0x64]	60188	1			T23	17		T24	10		T26	10
valid_sources[0x65]	53031	1			T23	6		T24	9		T26	11
valid_sources[0x66]	51008	1			T23	3		T24	8		T26	12
valid_sources[0x67]	54161	1			T23	13		T24	12		T26	10
valid_sources[0x68]	53691	1			T23	3		T24	10		T26	14
valid_sources[0x69]	54973	1			T23	3		T24	10		T26	16
valid_sources[0x6a]	55024	1			T23	2		T24	14		T25	3
valid_sources[0x6b]	50503	1			T23	7		T24	7		T26	18
valid_sources[0x6c]	57722	1			T23	8		T24	8		T26	13
valid_sources[0x6d]	53912	1			T23	9		T24	13		T26	4
valid_sources[0x6e]	54629	1			T23	8		T24	6		T26	20
valid_sources[0x6f]	57670	1			T21	17		T23	9		T24	7
valid_sources[0x70]	56719	1			T23	8		T24	13		T26	17
valid_sources[0x71]	52337	1			T23	21		T24	5		T12	7
valid_sources[0x72]	59626	1			T23	7		T24	14		T26	23
valid_sources[0x73]	53235	1			T21	5		T23	5		T24	6
valid_sources[0x74]	54365	1			T23	10		T24	5		T26	9
valid_sources[0x75]	57027	1			T23	12		T24	9		T25	7
valid_sources[0x76]	52331	1			T23	13		T24	11		T26	12
valid_sources[0x77]	52629	1			T23	8		T24	15		T25	3
valid_sources[0x78]	56483	1			T21	8		T23	2		T24	6
valid_sources[0x79]	195823	1			T23	2		T24	4		T26	12
valid_sources[0x7a]	52824	1			T23	9		T24	10		T25	1
valid_sources[0x7b]	54078	1			T23	14		T24	4		T25	1
valid_sources[0x7c]	54806	1			T23	15		T24	4		T26	7
valid_sources[0x7d]	55714	1			T23	10		T24	5		T25	1
valid_sources[0x7e]	76410	1			T21	5		T23	6		T24	8
valid_sources[0x7f]	50521	1			T23	7		T24	7		T26	5
valid_sources[0x80]	54206	1			T21	2		T23	3		T24	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3546117

1

T21

20

T22

1

T23

877

values[0x0]

all_enables

biggest_size

4565179

1

T21

111

T23

302

T24

133

values[0x1]

all_enables

biggest_size

4562510

1

T21

112

T22

2

T23

310