Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	140181185	0	0	0
ctrl_en_input_filter_rd_A	140181185	111357	0	0
intr_ctrl_en_falling_rd_A	140181185	113936	0	0
intr_ctrl_en_lvlhigh_rd_A	140181185	109770	0	0
intr_ctrl_en_lvllow_rd_A	140181185	115246	0	0
intr_ctrl_en_rising_rd_A	140181185	112025	0	0
intr_enable_rd_A	140181185	111376	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140181185	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140181185	111357	0	0
T1	8394	25	0	0
T2	36387	325	0	0
T3	0	119	0	0
T4	0	272	0	0
T5	0	5668	0	0
T6	0	82	0	0
T7	0	2311	0	0
T8	0	5243	0	0
T9	0	8	0	0
T10	0	1365	0	0
T11	8694	0	0	0
T12	5834	0	0	0
T13	1116	0	0	0
T14	1047	0	0	0
T15	2599	0	0	0
T16	3269	0	0	0
T17	4381	0	0	0
T18	8895	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140181185	113936	0	0
T1	8394	21	0	0
T2	36387	281	0	0
T3	0	95	0	0
T4	0	288	0	0
T5	0	5693	0	0
T6	0	88	0	0
T7	0	2514	0	0
T8	0	5433	0	0
T10	0	1444	0	0
T11	8694	0	0	0
T12	5834	0	0	0
T13	1116	0	0	0
T14	1047	0	0	0
T15	2599	0	0	0
T16	3269	0	0	0
T17	4381	0	0	0
T18	8895	0	0	0
T19	0	33828	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140181185	109770	0	0
T1	8394	43	0	0
T2	36387	284	0	0
T3	0	58	0	0
T4	0	319	0	0
T5	0	5561	0	0
T6	0	101	0	0
T7	0	2443	0	0
T8	0	5342	0	0
T10	0	1472	0	0
T11	8694	0	0	0
T12	5834	0	0	0
T13	1116	0	0	0
T14	1047	0	0	0
T15	2599	0	0	0
T16	3269	0	0	0
T17	4381	0	0	0
T18	8895	0	0	0
T20	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140181185	115246	0	0
T1	8394	29	0	0
T2	36387	347	0	0
T3	0	83	0	0
T4	0	215	0	0
T5	0	5587	0	0
T6	0	133	0	0
T7	0	2577	0	0
T8	0	5642	0	0
T10	0	1473	0	0
T11	8694	0	0	0
T12	5834	0	0	0
T13	1116	0	0	0
T14	1047	0	0	0
T15	2599	0	0	0
T16	3269	0	0	0
T17	4381	0	0	0
T18	8895	0	0	0
T19	0	34391	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140181185	112025	0	0
T1	8394	38	0	0
T2	36387	342	0	0
T3	0	127	0	0
T4	0	191	0	0
T5	0	5513	0	0
T6	0	112	0	0
T7	0	2457	0	0
T8	0	5308	0	0
T10	0	1482	0	0
T11	8694	0	0	0
T12	5834	0	0	0
T13	1116	0	0	0
T14	1047	0	0	0
T15	2599	0	0	0
T16	3269	0	0	0
T17	4381	0	0	0
T18	8895	0	0	0
T19	0	32066	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140181185	111376	0	0
T1	8394	41	0	0
T2	36387	288	0	0
T3	0	78	0	0
T4	0	221	0	0
T5	0	5865	0	0
T6	0	155	0	0
T7	0	2359	0	0
T8	0	5769	0	0
T10	0	1424	0	0
T11	8694	0	0	0
T12	5834	0	0	0
T13	1116	0	0	0
T14	1047	0	0	0
T15	2599	0	0	0
T16	3269	0	0	0
T17	4381	0	0	0
T18	8895	0	0	0
T20	0	2	0	0