Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3160936	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13762740

1

T35

431

T36

280

T37

196

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6847727	1			T35	237		T36	82		T37	46
values[0x0]	4962566	1			T35	163		T36	122		T37	89
values[0x1]	5113383	1			T35	155		T36	122		T37	86

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2439371	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14484305

1

T35

455

T36

288

T37

198

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	61260	1			T35	4		T39	1272		T41	1
valid_sources[0x01]	70925	1			T35	4		T37	2		T39	1318
valid_sources[0x02]	64338	1			T35	3		T39	1310		T45	9
valid_sources[0x03]	57616	1			T35	1		T37	1		T39	1302
valid_sources[0x04]	58609	1			T35	2		T37	1		T39	1328
valid_sources[0x05]	63664	1			T35	4		T37	2		T39	1314
valid_sources[0x06]	69479	1			T35	3		T37	1		T39	1303
valid_sources[0x07]	59539	1			T35	2		T39	1351		T41	1
valid_sources[0x08]	73206	1			T37	1		T39	1289		T44	2
valid_sources[0x09]	71270	1			T35	1		T37	4		T39	1257
valid_sources[0x0a]	70867	1			T35	2		T39	1191		T41	1
valid_sources[0x0b]	65902	1			T35	1		T37	2		T39	1296
valid_sources[0x0c]	64043	1			T35	1		T37	4		T39	1309
valid_sources[0x0d]	63595	1			T35	2		T37	1		T39	1273
valid_sources[0x0e]	60939	1			T37	1		T39	1347		T41	1
valid_sources[0x0f]	193781	1			T35	2		T37	2		T39	1250
valid_sources[0x10]	161727	1			T35	4		T37	5		T39	1323
valid_sources[0x11]	131717	1			T35	5		T37	1		T39	1327
valid_sources[0x12]	58840	1			T39	1364		T41	1		T45	5
valid_sources[0x13]	63599	1			T39	1339		T41	1		T45	16
valid_sources[0x14]	173000	1			T39	1326		T55	1		T45	9
valid_sources[0x15]	63814	1			T35	1		T39	1321		T44	1
valid_sources[0x16]	58589	1			T37	2		T39	1226		T44	1
valid_sources[0x17]	60510	1			T37	1		T39	1308		T41	3
valid_sources[0x18]	59549	1			T35	4		T37	2		T39	1254
valid_sources[0x19]	60699	1			T35	4		T37	1		T39	1265
valid_sources[0x1a]	61005	1			T37	1		T39	1304		T41	1
valid_sources[0x1b]	59683	1			T35	7		T39	1393		T41	2
valid_sources[0x1c]	60163	1			T35	11		T39	1358		T45	11
valid_sources[0x1d]	63031	1			T35	2		T39	1374		T44	1
valid_sources[0x1e]	63375	1			T35	1		T39	1231		T44	1
valid_sources[0x1f]	64931	1			T37	2		T39	1275		T41	2
valid_sources[0x20]	58556	1			T35	3		T39	1291		T41	2
valid_sources[0x21]	61932	1			T37	1		T39	1391		T45	8
valid_sources[0x22]	63460	1			T35	1		T37	2		T39	1259
valid_sources[0x23]	65530	1			T39	1319		T41	4		T45	9
valid_sources[0x24]	62120	1			T35	5		T39	1226		T44	3
valid_sources[0x25]	57586	1			T35	1		T37	2		T39	1317
valid_sources[0x26]	64609	1			T35	1		T39	1382		T41	2
valid_sources[0x27]	64677	1			T35	1		T39	1275		T44	4
valid_sources[0x28]	61022	1			T37	1		T39	1324		T44	1
valid_sources[0x29]	61049	1			T37	2		T39	1260		T41	2
valid_sources[0x2a]	60932	1			T35	2		T37	3		T39	1248
valid_sources[0x2b]	61259	1			T35	1		T37	1		T39	1254
valid_sources[0x2c]	55210	1			T37	1		T39	1342		T44	1
valid_sources[0x2d]	68277	1			T35	2		T37	2		T39	1298
valid_sources[0x2e]	152515	1			T35	8		T39	1235		T41	6
valid_sources[0x2f]	134578	1			T35	1		T37	1		T39	1339
valid_sources[0x30]	61074	1			T39	1366		T41	1		T45	7
valid_sources[0x31]	66784	1			T35	1		T38	4132		T39	1359
valid_sources[0x32]	58087	1			T35	2		T37	1		T39	1258
valid_sources[0x33]	59692	1			T35	3		T39	1324		T41	1
valid_sources[0x34]	64281	1			T35	3		T37	1		T39	1298
valid_sources[0x35]	64528	1			T35	5		T37	1		T39	1306
valid_sources[0x36]	62858	1			T35	1		T37	2		T39	1283
valid_sources[0x37]	64208	1			T35	8		T39	1379		T41	1
valid_sources[0x38]	61404	1			T35	1		T39	1256		T45	2
valid_sources[0x39]	58444	1			T35	2		T37	2		T39	1282
valid_sources[0x3a]	56954	1			T39	1254		T41	4		T45	13
valid_sources[0x3b]	57005	1			T35	3		T37	2		T39	1304
valid_sources[0x3c]	57742	1			T35	5		T39	1276		T41	3
valid_sources[0x3d]	63614	1			T35	1		T39	1362		T45	20
valid_sources[0x3e]	53709	1			T35	2		T39	1299		T41	4
valid_sources[0x3f]	63111	1			T35	4		T37	1		T39	1262
valid_sources[0x40]	57287	1			T35	2		T37	1		T39	1411
valid_sources[0x41]	61114	1			T35	5		T39	1332		T41	1
valid_sources[0x42]	64856	1			T35	1		T39	1231		T41	2
valid_sources[0x43]	63383	1			T35	1		T39	1243		T41	4
valid_sources[0x44]	65233	1			T35	3		T37	2		T39	1270
valid_sources[0x45]	65213	1			T35	3		T37	1		T39	1293
valid_sources[0x46]	60953	1			T39	1280		T41	1		T45	15
valid_sources[0x47]	71277	1			T37	1		T39	1332		T44	1
valid_sources[0x48]	60725	1			T35	4		T37	3		T39	1281
valid_sources[0x49]	68246	1			T35	4		T39	1398		T41	4
valid_sources[0x4a]	63940	1			T35	2		T37	2		T39	1347
valid_sources[0x4b]	62412	1			T35	1		T37	1		T39	1305
valid_sources[0x4c]	64182	1			T35	2		T39	1357		T44	1
valid_sources[0x4d]	62742	1			T35	7		T37	3		T39	1254
valid_sources[0x4e]	56600	1			T37	1		T39	1294		T41	1
valid_sources[0x4f]	61471	1			T35	1		T37	1		T39	1291
valid_sources[0x50]	64875	1			T35	1		T39	1255		T45	3
valid_sources[0x51]	56748	1			T39	1330		T44	1		T45	14
valid_sources[0x52]	58654	1			T35	3		T39	1315		T41	2
valid_sources[0x53]	54920	1			T35	2		T37	3		T39	1305
valid_sources[0x54]	66600	1			T35	7		T39	1306		T44	2
valid_sources[0x55]	60754	1			T37	1		T39	1320		T41	3
valid_sources[0x56]	66090	1			T35	4		T39	1251		T44	3
valid_sources[0x57]	60048	1			T39	1304		T45	20		T118	15
valid_sources[0x58]	61024	1			T35	4		T37	4		T39	1322
valid_sources[0x59]	63449	1			T35	6		T39	1273		T45	10
valid_sources[0x5a]	72660	1			T35	4		T37	1		T39	1302
valid_sources[0x5b]	59862	1			T35	1		T39	1320		T41	4
valid_sources[0x5c]	57927	1			T35	1		T39	1175		T44	2
valid_sources[0x5d]	58507	1			T35	1		T37	1		T39	1353
valid_sources[0x5e]	57713	1			T35	6		T37	1		T39	1308
valid_sources[0x5f]	62093	1			T35	1		T37	1		T39	1268
valid_sources[0x60]	70717	1			T35	1		T37	1		T39	1278
valid_sources[0x61]	57791	1			T39	1289		T45	12		T114	1
valid_sources[0x62]	62203	1			T35	2		T37	1		T39	1228
valid_sources[0x63]	62610	1			T35	4		T39	1353		T45	8
valid_sources[0x64]	63684	1			T35	2		T37	1		T39	1274
valid_sources[0x65]	94005	1			T35	4		T39	1313		T45	7
valid_sources[0x66]	58889	1			T35	2		T39	1355		T41	5
valid_sources[0x67]	63437	1			T35	3		T39	1289		T41	2
valid_sources[0x68]	63827	1			T35	1		T37	1		T39	1180
valid_sources[0x69]	67777	1			T39	1333		T41	5		T44	1
valid_sources[0x6a]	62165	1			T35	1		T39	1284		T41	3
valid_sources[0x6b]	59173	1			T35	4		T39	1244		T41	1
valid_sources[0x6c]	62748	1			T35	1		T37	2		T39	1270
valid_sources[0x6d]	55741	1			T35	2		T39	1248		T41	3
valid_sources[0x6e]	85867	1			T35	3		T37	1		T39	1257
valid_sources[0x6f]	59658	1			T35	3		T37	1		T39	1281
valid_sources[0x70]	55201	1			T35	1		T37	1		T39	1265
valid_sources[0x71]	66837	1			T37	1		T39	1297		T45	11
valid_sources[0x72]	65410	1			T35	9		T37	4		T39	1315
valid_sources[0x73]	60258	1			T35	6		T37	1		T39	1374
valid_sources[0x74]	59592	1			T35	1		T39	1328		T41	1
valid_sources[0x75]	60444	1			T35	2		T39	1284		T41	1
valid_sources[0x76]	64219	1			T35	12		T39	1285		T41	1
valid_sources[0x77]	60426	1			T35	3		T37	2		T39	1284
valid_sources[0x78]	58995	1			T35	1		T37	1		T39	1291
valid_sources[0x79]	172874	1			T35	5		T37	2		T39	1303
valid_sources[0x7a]	64708	1			T35	3		T37	1		T39	1228
valid_sources[0x7b]	64698	1			T35	5		T39	1268		T41	5
valid_sources[0x7c]	62562	1			T35	1		T39	1335		T41	3
valid_sources[0x7d]	59245	1			T35	2		T37	1		T39	1302
valid_sources[0x7e]	75466	1			T35	1		T37	1		T39	1374
valid_sources[0x7f]	69317	1			T35	2		T39	1271		T41	3
valid_sources[0x80]	69123	1			T35	1		T39	1372		T41	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3877582

1

T35

113

T36

36

T37

21

values[0x0]

all_enables

biggest_size

4946367

1

T35

163

T36

122

T37

89

values[0x1]

all_enables

biggest_size

4938791

1

T35

155

T36

122

T37

86