Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	138576219	0	0	0
ctrl_en_input_filter_rd_A	138576219	100209	0	0
intr_ctrl_en_falling_rd_A	138576219	105410	0	0
intr_ctrl_en_lvlhigh_rd_A	138576219	98488	0	0
intr_ctrl_en_lvllow_rd_A	138576219	104146	0	0
intr_ctrl_en_rising_rd_A	138576219	98764	0	0
intr_enable_rd_A	138576219	98713	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138576219	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138576219	100209	0	0
T1	8970	16	0	0
T2	0	10	0	0
T3	0	2	0	0
T4	0	3610	0	0
T5	0	1	0	0
T6	0	145	0	0
T7	0	3	0	0
T8	0	2253	0	0
T9	0	183	0	0
T10	0	171	0	0
T11	44916	0	0	0
T12	4785	0	0	0
T13	3658	0	0	0
T14	1829	0	0	0
T15	3252	0	0	0
T16	1635	0	0	0
T17	7724	0	0	0
T18	6909	0	0	0
T19	8099	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138576219	105410	0	0
T1	8970	39	0	0
T4	0	3640	0	0
T6	0	166	0	0
T8	0	2295	0	0
T9	0	144	0	0
T10	0	97	0	0
T11	44916	0	0	0
T12	4785	0	0	0
T13	3658	0	0	0
T14	1829	0	0	0
T15	3252	0	0	0
T16	1635	0	0	0
T17	7724	0	0	0
T18	6909	0	0	0
T19	8099	0	0	0
T20	0	314	0	0
T21	0	1761	0	0
T22	0	17	0	0
T23	0	10	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138576219	98488	0	0
T1	8970	23	0	0
T2	0	8	0	0
T4	0	3874	0	0
T6	0	169	0	0
T8	0	2232	0	0
T9	0	162	0	0
T10	0	131	0	0
T11	44916	0	0	0
T12	4785	0	0	0
T13	3658	0	0	0
T14	1829	0	0	0
T15	3252	0	0	0
T16	1635	0	0	0
T17	7724	0	0	0
T18	6909	0	0	0
T19	8099	3	0	0
T20	0	206	0	0
T24	0	2	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138576219	104146	0	0
T1	8970	23	0	0
T4	0	3947	0	0
T5	0	2	0	0
T6	0	163	0	0
T8	0	2227	0	0
T9	0	232	0	0
T10	0	112	0	0
T11	44916	0	0	0
T12	4785	0	0	0
T13	3658	0	0	0
T14	1829	0	0	0
T15	3252	0	0	0
T16	1635	0	0	0
T17	7724	0	0	0
T18	6909	0	0	0
T19	8099	5	0	0
T20	0	134	0	0
T21	0	1868	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138576219	98764	0	0
T1	0	40	0	0
T2	0	4	0	0
T3	0	2	0	0
T4	0	3680	0	0
T5	0	7	0	0
T6	0	183	0	0
T7	0	1	0	0
T8	0	2265	0	0
T19	0	2	0	0
T25	3281	5	0	0
T26	3076	0	0	0
T27	8141	0	0	0
T28	1425	0	0	0
T29	2920	0	0	0
T30	2116	0	0	0
T31	56758	0	0	0
T32	8371	0	0	0
T33	8071	0	0	0
T34	2333	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138576219	98713	0	0
T1	8970	22	0	0
T4	0	3859	0	0
T5	0	6	0	0
T6	0	152	0	0
T8	0	2279	0	0
T9	0	200	0	0
T10	0	147	0	0
T11	44916	0	0	0
T12	4785	0	0	0
T13	3658	0	0	0
T14	1829	0	0	0
T15	3252	0	0	0
T16	1635	0	0	0
T17	7724	0	0	0
T18	6909	0	0	0
T19	8099	6	0	0
T20	0	192	0	0
T21	0	1912	0	0