Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3874215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17444430

1

T22

142

T23

839

T24

378

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8475352	1			T22	20		T23	380		T24	51
values[0x0]	6309891	1			T22	66		T23	332		T24	189
values[0x1]	6533402	1			T22	62		T23	307		T24	163

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2974110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18344535

1

T22

145

T23

878

T24

381

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	78435	1			T22	1		T23	9		T29	3
valid_sources[0x01]	77915	1			T23	3		T27	1		T29	1
valid_sources[0x02]	80085	1			T23	1		T27	1		T29	3
valid_sources[0x03]	138834	1			T22	1		T23	5		T29	1
valid_sources[0x04]	79667	1			T22	2		T23	7		T30	2
valid_sources[0x05]	73825	1			T23	1		T25	1		T27	1
valid_sources[0x06]	151526	1			T23	6		T29	6		T30	2
valid_sources[0x07]	81844	1			T22	2		T23	3		T29	2
valid_sources[0x08]	79142	1			T23	2		T29	6		T30	5
valid_sources[0x09]	79272	1			T23	1		T25	2		T27	1
valid_sources[0x0a]	215732	1			T23	8		T27	1		T29	3
valid_sources[0x0b]	222015	1			T23	4		T29	4		T30	1
valid_sources[0x0c]	73574	1			T23	1		T25	10		T27	1
valid_sources[0x0d]	77659	1			T23	5		T25	1		T27	2
valid_sources[0x0e]	76337	1			T23	4		T27	3		T48	15
valid_sources[0x0f]	82839	1			T23	2		T29	1		T30	1
valid_sources[0x10]	76200	1			T22	1		T23	1		T25	6
valid_sources[0x11]	96576	1			T23	3		T25	2		T48	19
valid_sources[0x12]	81037	1			T23	3		T25	1		T27	3
valid_sources[0x13]	74603	1			T22	1		T29	6		T30	3
valid_sources[0x14]	78058	1			T22	1		T23	1		T25	1
valid_sources[0x15]	76942	1			T23	2		T25	1		T27	1
valid_sources[0x16]	84993	1			T22	2		T23	2		T25	1
valid_sources[0x17]	78206	1			T23	5		T27	3		T29	2
valid_sources[0x18]	85454	1			T22	1		T23	4		T29	4
valid_sources[0x19]	79765	1			T23	14		T27	2		T29	4
valid_sources[0x1a]	196246	1			T22	1		T23	4		T27	1
valid_sources[0x1b]	85805	1			T23	4		T30	1		T48	19
valid_sources[0x1c]	229279	1			T22	1		T23	5		T27	1
valid_sources[0x1d]	81069	1			T22	3		T23	4		T25	2
valid_sources[0x1e]	79134	1			T23	2		T27	2		T29	4
valid_sources[0x1f]	76396	1			T22	1		T23	5		T25	2
valid_sources[0x20]	76163	1			T22	1		T23	3		T29	2
valid_sources[0x21]	75702	1			T23	4		T29	1		T30	2
valid_sources[0x22]	78886	1			T22	1		T25	1		T27	2
valid_sources[0x23]	79771	1			T23	1		T29	4		T31	4
valid_sources[0x24]	73578	1			T23	4		T27	2		T29	1
valid_sources[0x25]	83512	1			T23	1		T27	3		T29	4
valid_sources[0x26]	93564	1			T23	1		T29	2		T30	3
valid_sources[0x27]	77479	1			T23	1		T27	1		T29	1
valid_sources[0x28]	74017	1			T22	3		T23	7		T27	1
valid_sources[0x29]	79058	1			T23	3		T29	2		T31	19
valid_sources[0x2a]	78205	1			T22	1		T25	1		T29	6
valid_sources[0x2b]	81980	1			T22	1		T23	3		T29	5
valid_sources[0x2c]	79698	1			T23	5		T27	2		T29	3
valid_sources[0x2d]	81282	1			T22	1		T23	9		T27	2
valid_sources[0x2e]	75435	1			T22	1		T23	5		T25	2
valid_sources[0x2f]	77954	1			T23	3		T25	1		T29	2
valid_sources[0x30]	78413	1			T23	10		T29	1		T30	1
valid_sources[0x31]	80878	1			T23	4		T27	2		T29	3
valid_sources[0x32]	76014	1			T22	4		T23	5		T25	2
valid_sources[0x33]	84134	1			T23	1		T27	3		T29	1
valid_sources[0x34]	83461	1			T22	1		T23	3		T27	1
valid_sources[0x35]	80230	1			T22	1		T23	8		T29	3
valid_sources[0x36]	77179	1			T22	2		T23	5		T25	1
valid_sources[0x37]	82387	1			T23	2		T27	2		T48	18
valid_sources[0x38]	84710	1			T23	3		T29	3		T30	3
valid_sources[0x39]	76191	1			T23	5		T25	2		T29	2
valid_sources[0x3a]	73725	1			T23	5		T29	2		T48	15
valid_sources[0x3b]	73501	1			T23	10		T29	2		T30	1
valid_sources[0x3c]	77756	1			T22	1		T23	4		T27	2
valid_sources[0x3d]	80303	1			T22	1		T23	4		T27	1
valid_sources[0x3e]	81190	1			T23	2		T27	3		T29	1
valid_sources[0x3f]	81213	1			T22	2		T23	2		T29	4
valid_sources[0x40]	74724	1			T23	7		T25	6		T29	2
valid_sources[0x41]	82784	1			T23	5		T27	3		T29	2
valid_sources[0x42]	83585	1			T23	1		T25	7		T29	4
valid_sources[0x43]	81339	1			T22	1		T23	4		T25	2
valid_sources[0x44]	73622	1			T23	8		T25	1		T27	1
valid_sources[0x45]	74345	1			T23	6		T27	3		T28	1
valid_sources[0x46]	79334	1			T23	4		T29	1		T48	20
valid_sources[0x47]	74133	1			T22	1		T23	1		T25	4
valid_sources[0x48]	81258	1			T22	1		T23	1		T25	2
valid_sources[0x49]	77808	1			T23	6		T29	2		T30	1
valid_sources[0x4a]	76653	1			T22	1		T23	3		T28	5
valid_sources[0x4b]	75866	1			T23	3		T25	1		T29	1
valid_sources[0x4c]	79761	1			T22	1		T23	3		T25	1
valid_sources[0x4d]	80484	1			T27	1		T28	1		T29	1
valid_sources[0x4e]	73212	1			T23	6		T25	1		T29	1
valid_sources[0x4f]	78015	1			T23	6		T27	1		T29	1
valid_sources[0x50]	142944	1			T22	1		T23	7		T48	15
valid_sources[0x51]	82591	1			T22	1		T23	6		T27	2
valid_sources[0x52]	80059	1			T22	3		T23	4		T25	1
valid_sources[0x53]	77726	1			T22	2		T23	14		T27	1
valid_sources[0x54]	79911	1			T22	1		T23	3		T27	2
valid_sources[0x55]	72207	1			T23	2		T25	5		T27	1
valid_sources[0x56]	82849	1			T22	1		T25	2		T29	1
valid_sources[0x57]	75480	1			T23	4		T25	2		T29	1
valid_sources[0x58]	79589	1			T23	3		T27	1		T29	8
valid_sources[0x59]	76724	1			T23	7		T29	1		T48	12
valid_sources[0x5a]	76965	1			T23	5		T27	1		T29	2
valid_sources[0x5b]	76831	1			T22	1		T23	4		T25	1
valid_sources[0x5c]	80179	1			T23	4		T29	4		T48	24
valid_sources[0x5d]	77203	1			T23	6		T30	4		T48	19
valid_sources[0x5e]	139093	1			T23	3		T29	4		T30	1
valid_sources[0x5f]	75584	1			T22	2		T23	6		T25	1
valid_sources[0x60]	74395	1			T22	1		T23	4		T29	1
valid_sources[0x61]	76874	1			T23	7		T27	1		T29	8
valid_sources[0x62]	86210	1			T23	2		T25	3		T27	5
valid_sources[0x63]	75556	1			T22	2		T23	6		T27	3
valid_sources[0x64]	78121	1			T23	9		T29	2		T30	2
valid_sources[0x65]	75450	1			T22	1		T23	5		T27	2
valid_sources[0x66]	77285	1			T22	1		T23	6		T27	1
valid_sources[0x67]	76524	1			T23	3		T25	2		T29	4
valid_sources[0x68]	197832	1			T22	1		T23	3		T29	6
valid_sources[0x69]	81469	1			T23	6		T25	7		T29	2
valid_sources[0x6a]	79484	1			T29	8		T30	1		T48	12
valid_sources[0x6b]	78380	1			T22	1		T23	3		T27	2
valid_sources[0x6c]	78373	1			T22	2		T23	5		T25	1
valid_sources[0x6d]	83965	1			T22	1		T23	6		T29	10
valid_sources[0x6e]	78544	1			T22	2		T23	3		T29	2
valid_sources[0x6f]	77242	1			T23	2		T27	1		T30	1
valid_sources[0x70]	81965	1			T22	1		T23	4		T27	2
valid_sources[0x71]	80076	1			T23	2		T25	2		T27	1
valid_sources[0x72]	78077	1			T23	1		T29	1		T30	3
valid_sources[0x73]	79045	1			T23	4		T25	2		T27	2
valid_sources[0x74]	79215	1			T23	2		T26	15		T27	1
valid_sources[0x75]	75867	1			T23	2		T27	1		T29	4
valid_sources[0x76]	81354	1			T22	2		T23	2		T25	6
valid_sources[0x77]	76528	1			T23	3		T27	2		T29	2
valid_sources[0x78]	77138	1			T29	3		T48	13		T52	2
valid_sources[0x79]	74584	1			T25	2		T29	4		T48	16
valid_sources[0x7a]	80986	1			T23	2		T29	5		T30	1
valid_sources[0x7b]	75010	1			T23	3		T29	3		T30	2
valid_sources[0x7c]	76899	1			T22	2		T23	3		T25	1
valid_sources[0x7d]	73039	1			T23	2		T27	1		T29	3
valid_sources[0x7e]	75800	1			T22	1		T23	4		T27	2
valid_sources[0x7f]	75593	1			T22	1		T25	2		T29	4
valid_sources[0x80]	80489	1			T23	5		T30	3		T31	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4871878

1

T22

14

T23

200

T24

26

values[0x0]

all_enables

biggest_size

6287129

1

T22

66

T23

332

T24

189

values[0x1]

all_enables

biggest_size

6285423

1

T22

62

T23

307

T24

163