Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	178052542	0	0	0
ctrl_en_input_filter_rd_A	178052542	74427	0	0
intr_ctrl_en_falling_rd_A	178052542	75395	0	0
intr_ctrl_en_lvlhigh_rd_A	178052542	73451	0	0
intr_ctrl_en_lvllow_rd_A	178052542	76415	0	0
intr_ctrl_en_rising_rd_A	178052542	75450	0	0
intr_enable_rd_A	178052542	74550	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178052542	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178052542	74427	0	0
T1	15272	135	0	0
T2	40722	285	0	0
T3	0	369	0	0
T4	0	151	0	0
T5	0	20080	0	0
T6	0	5971	0	0
T7	0	4	0	0
T8	0	2	0	0
T9	0	13134	0	0
T10	0	93	0	0
T11	10049	0	0	0
T12	6175	0	0	0
T13	4595	0	0	0
T14	2765	0	0	0
T15	11851	0	0	0
T16	8383	0	0	0
T17	6493	0	0	0
T18	1311	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178052542	75395	0	0
T1	15272	115	0	0
T2	40722	313	0	0
T3	0	339	0	0
T4	0	167	0	0
T5	0	20881	0	0
T6	0	6118	0	0
T7	0	2	0	0
T9	0	13507	0	0
T10	0	112	0	0
T11	10049	0	0	0
T12	6175	0	0	0
T13	4595	0	0	0
T14	2765	0	0	0
T15	11851	0	0	0
T16	8383	0	0	0
T17	6493	0	0	0
T18	1311	0	0	0
T19	0	8	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178052542	73451	0	0
T1	15272	128	0	0
T2	40722	323	0	0
T3	0	411	0	0
T4	0	160	0	0
T5	0	19658	0	0
T6	0	6123	0	0
T9	0	12927	0	0
T10	0	116	0	0
T11	10049	0	0	0
T12	6175	0	0	0
T13	4595	0	0	0
T14	2765	0	0	0
T15	11851	0	0	0
T16	8383	0	0	0
T17	6493	0	0	0
T18	1311	0	0	0
T20	0	45	0	0
T21	0	2322	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178052542	76415	0	0
T1	15272	134	0	0
T2	40722	302	0	0
T3	0	398	0	0
T4	0	148	0	0
T5	0	20625	0	0
T6	0	5830	0	0
T7	0	7	0	0
T9	0	14263	0	0
T10	0	72	0	0
T11	10049	0	0	0
T12	6175	0	0	0
T13	4595	0	0	0
T14	2765	0	0	0
T15	11851	0	0	0
T16	8383	0	0	0
T17	6493	0	0	0
T18	1311	0	0	0
T19	0	6	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178052542	75450	0	0
T1	15272	158	0	0
T2	40722	264	0	0
T3	0	404	0	0
T4	0	162	0	0
T5	0	19645	0	0
T6	0	6135	0	0
T7	0	5	0	0
T8	0	2	0	0
T9	0	13363	0	0
T10	0	109	0	0
T11	10049	0	0	0
T12	6175	0	0	0
T13	4595	0	0	0
T14	2765	0	0	0
T15	11851	0	0	0
T16	8383	0	0	0
T17	6493	0	0	0
T18	1311	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178052542	74550	0	0
T1	15272	129	0	0
T2	40722	321	0	0
T3	0	423	0	0
T4	0	149	0	0
T5	0	20290	0	0
T6	0	6348	0	0
T7	0	3	0	0
T8	0	2	0	0
T9	0	12965	0	0
T10	0	111	0	0
T11	10049	0	0	0
T12	6175	0	0	0
T13	4595	0	0	0
T14	2765	0	0	0
T15	11851	0	0	0
T16	8383	0	0	0
T17	6493	0	0	0
T18	1311	0	0	0