Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3033844	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13557331

1

T24

232

T25

68

T26

2658

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6633566	1			T24	48		T25	49		T26	1629
values[0x0]	4893016	1			T24	102		T25	21		T26	912
values[0x1]	5064593	1			T24	106		T25	23		T26	952

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2330141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14261034

1

T24

235

T25

69

T26

2810

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	60071	1			T25	1		T26	14		T1	14
valid_sources[0x01]	56985	1			T26	13		T1	16		T11	7
valid_sources[0x02]	59620	1			T26	19		T1	19		T14	2
valid_sources[0x03]	58987	1			T25	1		T26	14		T1	4
valid_sources[0x04]	63689	1			T25	1		T26	9		T1	9
valid_sources[0x05]	58341	1			T26	14		T1	12		T15	5
valid_sources[0x06]	59583	1			T25	1		T26	13		T1	12
valid_sources[0x07]	64961	1			T25	1		T26	10		T1	11
valid_sources[0x08]	57919	1			T26	21		T1	8		T17	21
valid_sources[0x09]	61720	1			T26	12		T1	14		T11	1
valid_sources[0x0a]	60629	1			T26	18		T1	19		T11	6
valid_sources[0x0b]	66718	1			T26	18		T1	13		T11	1
valid_sources[0x0c]	62992	1			T26	13		T1	16		T15	4
valid_sources[0x0d]	68238	1			T26	17		T1	19		T11	1
valid_sources[0x0e]	63615	1			T24	256		T26	16		T1	14
valid_sources[0x0f]	57192	1			T26	15		T1	8		T11	4
valid_sources[0x10]	58817	1			T26	18		T1	11		T11	11
valid_sources[0x11]	58735	1			T25	1		T26	10		T1	13
valid_sources[0x12]	63649	1			T26	13		T1	13		T12	1
valid_sources[0x13]	60462	1			T25	2		T26	15		T1	8
valid_sources[0x14]	58511	1			T25	1		T26	13		T1	15
valid_sources[0x15]	62600	1			T26	10		T1	14		T11	1
valid_sources[0x16]	58569	1			T25	1		T26	11		T1	10
valid_sources[0x17]	61739	1			T26	17		T1	9		T11	6
valid_sources[0x18]	57325	1			T25	1		T26	11		T1	10
valid_sources[0x19]	64334	1			T26	14		T1	14		T11	8
valid_sources[0x1a]	62032	1			T26	11		T1	16		T15	1
valid_sources[0x1b]	59579	1			T26	11		T1	9		T14	2
valid_sources[0x1c]	63809	1			T25	2		T26	12		T1	12
valid_sources[0x1d]	64590	1			T26	14		T1	13		T11	6
valid_sources[0x1e]	60454	1			T25	3		T26	14		T1	19
valid_sources[0x1f]	62226	1			T25	1		T26	19		T1	8
valid_sources[0x20]	66032	1			T26	4		T1	20		T11	5
valid_sources[0x21]	59173	1			T25	1		T26	14		T1	10
valid_sources[0x22]	199327	1			T26	10		T1	14		T11	3
valid_sources[0x23]	70176	1			T26	16		T1	14		T14	1
valid_sources[0x24]	61630	1			T25	2		T26	12		T1	19
valid_sources[0x25]	71519	1			T26	15		T1	10		T12	6
valid_sources[0x26]	64433	1			T26	9		T1	11		T11	4
valid_sources[0x27]	57656	1			T25	1		T26	9		T1	14
valid_sources[0x28]	64395	1			T25	1		T26	25		T1	16
valid_sources[0x29]	61383	1			T26	18		T1	11		T15	21
valid_sources[0x2a]	58027	1			T26	19		T1	12		T11	4
valid_sources[0x2b]	57919	1			T26	12		T1	8		T14	1
valid_sources[0x2c]	59151	1			T25	1		T26	14		T1	15
valid_sources[0x2d]	61179	1			T26	28		T1	13		T11	2
valid_sources[0x2e]	59582	1			T25	1		T26	7		T1	6
valid_sources[0x2f]	192643	1			T26	7		T1	13		T14	2
valid_sources[0x30]	56282	1			T25	1		T26	16		T1	15
valid_sources[0x31]	62914	1			T26	10		T1	5		T11	13
valid_sources[0x32]	59761	1			T26	16		T1	7		T14	4
valid_sources[0x33]	59180	1			T26	11		T1	11		T15	7
valid_sources[0x34]	60952	1			T26	11		T1	15		T12	2
valid_sources[0x35]	59898	1			T25	1		T26	9		T1	12
valid_sources[0x36]	58008	1			T25	1		T26	12		T1	10
valid_sources[0x37]	65294	1			T25	1		T26	13		T1	10
valid_sources[0x38]	57616	1			T25	1		T26	7		T1	10
valid_sources[0x39]	60195	1			T26	14		T1	18		T17	26
valid_sources[0x3a]	61957	1			T26	16		T1	9		T14	1
valid_sources[0x3b]	56481	1			T26	12		T1	15		T12	5
valid_sources[0x3c]	61098	1			T26	9		T1	6		T11	1
valid_sources[0x3d]	117676	1			T26	10		T1	16		T14	1
valid_sources[0x3e]	61917	1			T26	13		T1	18		T11	1
valid_sources[0x3f]	62095	1			T26	8		T1	8		T11	5
valid_sources[0x40]	56534	1			T25	1		T26	15		T1	12
valid_sources[0x41]	60613	1			T26	29		T1	10		T15	9
valid_sources[0x42]	147071	1			T26	11		T1	5		T11	2
valid_sources[0x43]	60432	1			T26	10		T1	9		T14	2
valid_sources[0x44]	58978	1			T26	14		T1	19		T11	3
valid_sources[0x45]	136193	1			T26	16		T1	11		T11	4
valid_sources[0x46]	61901	1			T26	12		T1	12		T11	10
valid_sources[0x47]	59720	1			T25	1		T26	26		T1	14
valid_sources[0x48]	56493	1			T26	15		T1	14		T14	1
valid_sources[0x49]	60405	1			T25	2		T26	17		T1	12
valid_sources[0x4a]	61574	1			T26	16		T1	13		T11	1
valid_sources[0x4b]	58337	1			T26	15		T1	17		T13	12
valid_sources[0x4c]	64655	1			T26	16		T1	11		T14	2
valid_sources[0x4d]	57250	1			T26	16		T1	8		T11	3
valid_sources[0x4e]	56404	1			T26	10		T1	12		T12	2
valid_sources[0x4f]	60143	1			T26	13		T1	10		T14	2
valid_sources[0x50]	61150	1			T26	18		T1	17		T12	3
valid_sources[0x51]	61421	1			T26	10		T1	18		T11	7
valid_sources[0x52]	132163	1			T25	1		T26	15		T1	12
valid_sources[0x53]	58309	1			T25	1		T26	8		T1	16
valid_sources[0x54]	58954	1			T26	11		T1	23		T14	5
valid_sources[0x55]	59699	1			T26	13		T1	12		T11	4
valid_sources[0x56]	66332	1			T26	11		T1	11		T15	5
valid_sources[0x57]	60617	1			T26	11		T1	10		T11	2
valid_sources[0x58]	64218	1			T26	9		T1	13		T11	16
valid_sources[0x59]	158937	1			T26	12		T1	7		T11	1
valid_sources[0x5a]	59186	1			T26	13		T1	15		T13	3
valid_sources[0x5b]	61367	1			T26	12		T1	12		T15	6
valid_sources[0x5c]	58217	1			T26	16		T1	11		T14	1
valid_sources[0x5d]	60756	1			T26	6		T1	14		T15	20
valid_sources[0x5e]	57316	1			T26	15		T1	13		T11	7
valid_sources[0x5f]	58780	1			T26	6		T1	14		T11	1
valid_sources[0x60]	67854	1			T25	3		T26	18		T1	10
valid_sources[0x61]	62863	1			T26	9		T1	16		T11	9
valid_sources[0x62]	62818	1			T26	10		T1	19		T14	1
valid_sources[0x63]	58457	1			T25	1		T26	17		T1	8
valid_sources[0x64]	56380	1			T25	2		T26	15		T1	8
valid_sources[0x65]	56018	1			T25	1		T26	20		T1	19
valid_sources[0x66]	58267	1			T26	12		T1	9		T14	1
valid_sources[0x67]	58696	1			T25	1		T26	17		T1	11
valid_sources[0x68]	60826	1			T26	15		T1	14		T14	2
valid_sources[0x69]	64297	1			T26	8		T1	16		T11	4
valid_sources[0x6a]	63716	1			T26	14		T1	14		T11	1
valid_sources[0x6b]	59996	1			T26	21		T1	11		T11	3
valid_sources[0x6c]	66469	1			T25	1		T26	17		T1	13
valid_sources[0x6d]	66578	1			T26	15		T1	10		T11	9
valid_sources[0x6e]	59091	1			T25	1		T26	10		T1	10
valid_sources[0x6f]	58649	1			T25	1		T26	19		T1	14
valid_sources[0x70]	67449	1			T26	10		T1	9		T11	8
valid_sources[0x71]	60573	1			T26	19		T1	14		T14	3
valid_sources[0x72]	59608	1			T26	13		T1	11		T11	11
valid_sources[0x73]	61121	1			T26	21		T1	11		T16	1
valid_sources[0x74]	65724	1			T26	12		T1	14		T14	1
valid_sources[0x75]	60885	1			T26	10		T1	20		T11	4
valid_sources[0x76]	62765	1			T25	1		T26	11		T1	13
valid_sources[0x77]	62495	1			T26	12		T1	13		T12	5
valid_sources[0x78]	66257	1			T26	11		T1	6		T14	1
valid_sources[0x79]	61404	1			T26	16		T1	8		T14	1
valid_sources[0x7a]	63620	1			T26	16		T1	13		T11	6
valid_sources[0x7b]	63690	1			T26	14		T1	16		T11	14
valid_sources[0x7c]	66292	1			T26	12		T1	8		T11	15
valid_sources[0x7d]	56999	1			T26	9		T1	14		T11	1
valid_sources[0x7e]	62275	1			T25	2		T26	14		T1	14
valid_sources[0x7f]	59243	1			T26	15		T1	15		T11	3
valid_sources[0x80]	56534	1			T26	8		T1	21		T11	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3807198

1

T24

24

T25

24

T26

794

values[0x0]

all_enables

biggest_size

4875395

1

T24

102

T25

21

T26

912

values[0x1]

all_enables

biggest_size

4874738

1

T24

106

T25

23

T26

952