Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	141228484	0	0	0
ctrl_en_input_filter_rd_A	141228484	69201	0	0
intr_ctrl_en_falling_rd_A	141228484	69847	0	0
intr_ctrl_en_lvlhigh_rd_A	141228484	69223	0	0
intr_ctrl_en_lvllow_rd_A	141228484	69992	0	0
intr_ctrl_en_rising_rd_A	141228484	70342	0	0
intr_enable_rd_A	141228484	68109	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141228484	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141228484	69201	0	0
T1	35729	263	0	0
T2	0	53	0	0
T3	0	1381	0	0
T4	0	30	0	0
T5	0	1270	0	0
T6	0	3891	0	0
T7	0	168	0	0
T8	0	1859	0	0
T9	0	3592	0	0
T10	0	8	0	0
T11	5032	0	0	0
T12	4435	0	0	0
T13	2424	0	0	0
T14	2199	0	0	0
T15	8775	0	0	0
T16	4869	0	0	0
T17	73431	0	0	0
T18	880	0	0	0
T19	11874	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141228484	69847	0	0
T1	35729	240	0	0
T2	0	79	0	0
T3	0	1293	0	0
T4	0	23	0	0
T5	0	1345	0	0
T6	0	4052	0	0
T7	0	164	0	0
T8	0	1724	0	0
T11	5032	0	0	0
T12	4435	0	0	0
T13	2424	0	0	0
T14	2199	0	0	0
T15	8775	0	0	0
T16	4869	0	0	0
T17	73431	0	0	0
T18	880	0	0	0
T19	11874	0	0	0
T20	0	5	0	0
T21	0	1	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141228484	69223	0	0
T1	35729	213	0	0
T2	0	80	0	0
T3	0	1323	0	0
T4	0	45	0	0
T5	0	1210	0	0
T6	0	4093	0	0
T7	0	183	0	0
T8	0	1860	0	0
T9	0	3348	0	0
T10	0	4	0	0
T11	5032	0	0	0
T12	4435	0	0	0
T13	2424	0	0	0
T14	2199	0	0	0
T15	8775	0	0	0
T16	4869	0	0	0
T17	73431	0	0	0
T18	880	0	0	0
T19	11874	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141228484	69992	0	0
T1	35729	243	0	0
T2	0	108	0	0
T3	0	1417	0	0
T4	0	49	0	0
T5	0	1404	0	0
T6	0	3986	0	0
T7	0	220	0	0
T8	0	1859	0	0
T11	5032	0	0	0
T12	4435	0	0	0
T13	2424	0	0	0
T14	2199	0	0	0
T15	8775	0	0	0
T16	4869	0	0	0
T17	73431	0	0	0
T18	880	0	0	0
T19	11874	0	0	0
T21	0	3	0	0
T22	0	2	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141228484	70342	0	0
T1	35729	265	0	0
T2	0	71	0	0
T3	0	1290	0	0
T4	0	39	0	0
T5	0	1261	0	0
T6	0	3881	0	0
T7	0	182	0	0
T8	0	1815	0	0
T9	0	3438	0	0
T11	5032	0	0	0
T12	4435	0	0	0
T13	2424	0	0	0
T14	2199	0	0	0
T15	8775	0	0	0
T16	4869	0	0	0
T17	73431	0	0	0
T18	880	0	0	0
T19	11874	0	0	0
T22	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141228484	68109	0	0
T1	35729	216	0	0
T2	0	36	0	0
T3	0	1328	0	0
T4	0	29	0	0
T5	0	1362	0	0
T6	0	3750	0	0
T7	0	172	0	0
T8	0	1859	0	0
T9	0	3321	0	0
T11	5032	0	0	0
T12	4435	0	0	0
T13	2424	0	0	0
T14	2199	0	0	0
T15	8775	0	0	0
T16	4869	0	0	0
T17	73431	0	0	0
T18	880	0	0	0
T19	11874	0	0	0
T23	0	391	0	0