Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4848193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21986536

1

T22

103

T23

80247

T24

201

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10642348	1			T22	12		T23	45833		T24	119
values[0x0]	7951207	1			T22	50		T23	28579		T24	66
values[0x1]	8241174	1			T22	46		T23	28800		T24	79

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3717339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

23117390

1

T22

105

T23

84831

T24

213

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	105822	1			T25	11		T26	5		T27	1
valid_sources[0x01]	103596	1			T25	6		T26	8		T30	1
valid_sources[0x02]	101176	1			T25	6		T26	7		T30	5
valid_sources[0x03]	106049	1			T25	8		T30	1		T117	1
valid_sources[0x04]	108948	1			T25	6		T118	4		T32	5
valid_sources[0x05]	108402	1			T25	6		T26	7		T117	3
valid_sources[0x06]	99590	1			T25	12		T30	4		T118	2
valid_sources[0x07]	98271	1			T25	9		T30	3		T118	2
valid_sources[0x08]	100514	1			T25	8		T26	1		T30	5
valid_sources[0x09]	101830	1			T25	12		T118	1		T117	1
valid_sources[0x0a]	97311	1			T25	10		T26	5		T30	1
valid_sources[0x0b]	110295	1			T25	12		T26	13		T27	2
valid_sources[0x0c]	101219	1			T25	7		T26	2		T30	4
valid_sources[0x0d]	98539	1			T25	4		T30	2		T118	1
valid_sources[0x0e]	94469	1			T25	11		T26	2		T118	1
valid_sources[0x0f]	96761	1			T25	2		T26	5		T30	3
valid_sources[0x10]	106847	1			T25	11		T30	7		T118	4
valid_sources[0x11]	102568	1			T25	10		T26	3		T118	1
valid_sources[0x12]	158070	1			T25	9		T27	1		T30	2
valid_sources[0x13]	111703	1			T25	9		T30	1		T118	3
valid_sources[0x14]	109023	1			T25	9		T26	1		T32	5
valid_sources[0x15]	92571	1			T25	9		T30	1		T32	1
valid_sources[0x16]	97277	1			T25	6		T30	3		T118	2
valid_sources[0x17]	100070	1			T25	14		T26	1		T30	3
valid_sources[0x18]	117058	1			T25	5		T30	5		T118	3
valid_sources[0x19]	107361	1			T25	11		T26	1		T28	16
valid_sources[0x1a]	112294	1			T25	14		T26	6		T30	1
valid_sources[0x1b]	109159	1			T25	11		T26	4		T30	3
valid_sources[0x1c]	100589	1			T25	12		T26	8		T30	6
valid_sources[0x1d]	90698	1			T25	8		T26	13		T30	1
valid_sources[0x1e]	95254	1			T25	4		T26	6		T30	1
valid_sources[0x1f]	95837	1			T25	6		T30	1		T32	2
valid_sources[0x20]	99338	1			T25	7		T26	4		T118	2
valid_sources[0x21]	103959	1			T25	9		T26	4		T30	1
valid_sources[0x22]	112536	1			T25	8		T30	2		T118	3
valid_sources[0x23]	104479	1			T25	11		T26	7		T30	1
valid_sources[0x24]	94809	1			T25	10		T26	5		T30	3
valid_sources[0x25]	101338	1			T25	7		T26	4		T30	3
valid_sources[0x26]	103706	1			T25	8		T26	7		T30	1
valid_sources[0x27]	102525	1			T25	7		T26	14		T30	4
valid_sources[0x28]	96100	1			T25	11		T26	7		T30	5
valid_sources[0x29]	99934	1			T25	10		T26	1		T30	1
valid_sources[0x2a]	101763	1			T25	6		T26	13		T30	1
valid_sources[0x2b]	108045	1			T25	14		T30	2		T118	3
valid_sources[0x2c]	92370	1			T25	10		T27	1		T118	1
valid_sources[0x2d]	101444	1			T25	6		T26	7		T118	1
valid_sources[0x2e]	101268	1			T25	6		T30	5		T117	1
valid_sources[0x2f]	108074	1			T25	10		T30	3		T32	2
valid_sources[0x30]	96185	1			T25	10		T26	5		T30	8
valid_sources[0x31]	213784	1			T23	103212		T25	6		T26	2
valid_sources[0x32]	110589	1			T25	5		T118	1		T32	2
valid_sources[0x33]	97979	1			T25	8		T30	1		T118	1
valid_sources[0x34]	98661	1			T25	6		T26	2		T118	1
valid_sources[0x35]	110174	1			T25	9		T30	7		T118	4
valid_sources[0x36]	102621	1			T25	3		T26	2		T118	2
valid_sources[0x37]	99080	1			T25	11		T30	2		T118	2
valid_sources[0x38]	100121	1			T25	8		T26	4		T30	2
valid_sources[0x39]	95405	1			T25	9		T26	5		T30	3
valid_sources[0x3a]	107221	1			T25	5		T26	1		T30	2
valid_sources[0x3b]	99683	1			T25	7		T26	7		T30	3
valid_sources[0x3c]	100669	1			T25	7		T30	1		T1	14
valid_sources[0x3d]	98283	1			T25	12		T27	1		T30	7
valid_sources[0x3e]	104081	1			T25	11		T30	3		T118	1
valid_sources[0x3f]	95355	1			T25	7		T26	6		T30	5
valid_sources[0x40]	99013	1			T25	9		T26	10		T30	2
valid_sources[0x41]	99719	1			T25	7		T30	3		T118	1
valid_sources[0x42]	97655	1			T25	12		T26	10		T30	2
valid_sources[0x43]	95698	1			T25	3		T27	1		T118	3
valid_sources[0x44]	113226	1			T25	5		T27	1		T30	1
valid_sources[0x45]	102261	1			T25	8		T26	1		T30	5
valid_sources[0x46]	102375	1			T25	4		T26	2		T30	3
valid_sources[0x47]	108481	1			T25	9		T26	22		T27	2
valid_sources[0x48]	108149	1			T25	5		T30	1		T118	1
valid_sources[0x49]	137265	1			T25	9		T26	2		T30	1
valid_sources[0x4a]	92576	1			T25	5		T26	5		T28	64
valid_sources[0x4b]	118999	1			T25	11		T30	1		T118	1
valid_sources[0x4c]	98528	1			T25	11		T26	2		T30	1
valid_sources[0x4d]	103580	1			T25	9		T26	9		T30	1
valid_sources[0x4e]	105194	1			T25	9		T26	1		T30	3
valid_sources[0x4f]	104733	1			T25	10		T30	3		T118	1
valid_sources[0x50]	107010	1			T25	9		T28	9		T30	1
valid_sources[0x51]	105308	1			T22	108		T24	264		T25	8
valid_sources[0x52]	108482	1			T25	10		T26	1		T30	2
valid_sources[0x53]	104724	1			T25	7		T26	17		T30	4
valid_sources[0x54]	103383	1			T25	11		T26	3		T30	1
valid_sources[0x55]	105338	1			T25	11		T26	2		T30	4
valid_sources[0x56]	97622	1			T25	10		T26	11		T30	2
valid_sources[0x57]	98793	1			T25	11		T26	10		T118	3
valid_sources[0x58]	99387	1			T25	8		T27	1		T118	1
valid_sources[0x59]	108009	1			T25	8		T26	7		T118	1
valid_sources[0x5a]	100486	1			T25	17		T30	1		T118	2
valid_sources[0x5b]	112647	1			T25	12		T30	3		T32	1
valid_sources[0x5c]	113578	1			T25	8		T26	4		T29	401
valid_sources[0x5d]	103823	1			T25	12		T26	4		T30	3
valid_sources[0x5e]	100522	1			T25	11		T26	2		T30	3
valid_sources[0x5f]	103873	1			T25	10		T26	1		T27	3
valid_sources[0x60]	98466	1			T25	12		T26	4		T30	5
valid_sources[0x61]	104167	1			T25	10		T26	5		T118	1
valid_sources[0x62]	98035	1			T25	12		T26	1		T32	5
valid_sources[0x63]	228064	1			T25	7		T30	1		T118	2
valid_sources[0x64]	107194	1			T25	3		T26	3		T118	2
valid_sources[0x65]	101890	1			T25	9		T26	9		T30	3
valid_sources[0x66]	104403	1			T25	10		T26	1		T30	2
valid_sources[0x67]	100611	1			T25	6		T26	9		T30	4
valid_sources[0x68]	103922	1			T25	13		T26	7		T27	1
valid_sources[0x69]	101106	1			T25	11		T27	2		T30	4
valid_sources[0x6a]	97412	1			T25	10		T26	9		T30	2
valid_sources[0x6b]	103876	1			T25	9		T30	2		T118	1
valid_sources[0x6c]	103778	1			T25	13		T26	3		T118	5
valid_sources[0x6d]	103922	1			T25	12		T30	6		T118	3
valid_sources[0x6e]	99253	1			T25	9		T118	4		T117	1
valid_sources[0x6f]	106311	1			T25	9		T30	3		T118	2
valid_sources[0x70]	103202	1			T25	8		T26	2		T117	4
valid_sources[0x71]	96931	1			T25	11		T30	2		T118	2
valid_sources[0x72]	104655	1			T25	11		T26	9		T30	1
valid_sources[0x73]	109836	1			T25	4		T26	5		T30	3
valid_sources[0x74]	109033	1			T25	3		T26	1		T30	1
valid_sources[0x75]	97446	1			T25	11		T26	1		T30	6
valid_sources[0x76]	105546	1			T25	5		T26	11		T30	1
valid_sources[0x77]	99638	1			T25	12		T26	7		T30	2
valid_sources[0x78]	102609	1			T25	6		T26	7		T27	1
valid_sources[0x79]	96097	1			T25	10		T27	2		T30	1
valid_sources[0x7a]	107014	1			T25	11		T30	2		T118	1
valid_sources[0x7b]	100910	1			T25	6		T118	3		T32	5
valid_sources[0x7c]	232513	1			T25	2		T26	5		T118	6
valid_sources[0x7d]	100502	1			T25	4		T118	1		T117	1
valid_sources[0x7e]	99798	1			T25	9		T30	3		T117	2
valid_sources[0x7f]	97254	1			T25	9		T26	7		T118	3
valid_sources[0x80]	114747	1			T25	8		T26	9		T30	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6139784

1

T22

7

T23

22868

T24

56

values[0x0]

all_enables

biggest_size

7922325

1

T22

50

T23

28579

T24

66

values[0x1]

all_enables

biggest_size

7924427

1

T22

46

T23

28800

T24

79