Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	204194137	0	0	0
ctrl_en_input_filter_rd_A	204194137	59512	0	0
intr_ctrl_en_falling_rd_A	204194137	61652	0	0
intr_ctrl_en_lvlhigh_rd_A	204194137	59722	0	0
intr_ctrl_en_lvllow_rd_A	204194137	62278	0	0
intr_ctrl_en_rising_rd_A	204194137	60255	0	0
intr_enable_rd_A	204194137	60187	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204194137	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204194137	59512	0	0
T1	37465	249	0	0
T2	0	152	0	0
T3	0	2795	0	0
T4	0	384	0	0
T5	0	6	0	0
T6	0	4	0	0
T7	0	1168	0	0
T8	0	152	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	856	0	0	0
T12	1500	0	0	0
T13	2499	0	0	0
T14	6899	0	0	0
T15	5567	0	0	0
T16	2305	0	0	0
T17	3458	0	0	0
T18	2196	0	0	0
T19	914	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204194137	61652	0	0
T1	37465	229	0	0
T2	0	159	0	0
T3	0	3034	0	0
T4	0	319	0	0
T5	0	3	0	0
T7	0	1303	0	0
T8	0	126	0	0
T10	0	11	0	0
T11	856	0	0	0
T12	1500	0	0	0
T13	2499	0	0	0
T14	6899	0	0	0
T15	5567	0	0	0
T16	2305	0	0	0
T17	3458	0	0	0
T18	2196	0	0	0
T19	914	0	0	0
T20	0	226	0	0
T21	0	333	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204194137	59722	0	0
T1	37465	186	0	0
T2	0	129	0	0
T3	0	3057	0	0
T4	0	341	0	0
T5	0	7	0	0
T6	0	3	0	0
T7	0	1221	0	0
T8	0	138	0	0
T10	0	6	0	0
T11	856	0	0	0
T12	1500	0	0	0
T13	2499	0	0	0
T14	6899	0	0	0
T15	5567	0	0	0
T16	2305	0	0	0
T17	3458	0	0	0
T18	2196	0	0	0
T19	914	0	0	0
T20	0	223	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204194137	62278	0	0
T1	37465	195	0	0
T2	0	167	0	0
T3	0	2846	0	0
T4	0	457	0	0
T6	0	6	0	0
T7	0	1157	0	0
T8	0	127	0	0
T9	0	1	0	0
T11	856	0	0	0
T12	1500	0	0	0
T13	2499	0	0	0
T14	6899	0	0	0
T15	5567	0	0	0
T16	2305	0	0	0
T17	3458	0	0	0
T18	2196	0	0	0
T19	914	0	0	0
T20	0	252	0	0
T21	0	381	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204194137	60255	0	0
T1	37465	272	0	0
T2	0	131	0	0
T3	0	2829	0	0
T4	0	426	0	0
T5	0	4	0	0
T6	0	15	0	0
T7	0	1214	0	0
T8	0	136	0	0
T11	856	0	0	0
T12	1500	0	0	0
T13	2499	5	0	0
T14	6899	0	0	0
T15	5567	0	0	0
T16	2305	0	0	0
T17	3458	0	0	0
T18	2196	0	0	0
T19	914	0	0	0
T20	0	202	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204194137	60187	0	0
T1	0	229	0	0
T2	0	129	0	0
T3	0	3064	0	0
T4	0	302	0	0
T6	0	4	0	0
T7	0	1091	0	0
T8	0	90	0	0
T10	0	4	0	0
T13	0	4	0	0
T22	4089	1	0	0
T23	567303	0	0	0
T24	4167	0	0	0
T25	8425	0	0	0
T26	7886	0	0	0
T27	2916	0	0	0
T28	1420	0	0	0
T29	7778	0	0	0
T30	5453	0	0	0
T31	8956	0	0	0