Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3432542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14964470

1

T24

4

T25

171

T26

216

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7434887	1			T24	1		T25	154		T26	50
values[0x0]	5393672	1			T24	4		T25	50		T26	84
values[0x1]	5568453	1			T24	7		T25	54		T26	111

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2649575	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15747437

1

T24

4

T25

190

T26

218

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	65119	1			T25	1		T12	1		T14	1
valid_sources[0x01]	72889	1			T2	4		T14	9		T15	244
valid_sources[0x02]	65593	1			T25	3		T2	16		T11	1
valid_sources[0x03]	76216	1			T12	2		T15	272		T18	10
valid_sources[0x04]	61221	1			T2	29		T15	251		T16	2
valid_sources[0x05]	69721	1			T25	1		T15	217		T18	24
valid_sources[0x06]	62450	1			T2	3		T15	276		T16	2
valid_sources[0x07]	72705	1			T15	273		T16	1		T18	19
valid_sources[0x08]	153764	1			T25	3		T2	17		T12	5
valid_sources[0x09]	69842	1			T25	1		T2	17		T15	238
valid_sources[0x0a]	71275	1			T12	3		T15	270		T18	17
valid_sources[0x0b]	73509	1			T24	2		T25	3		T2	22
valid_sources[0x0c]	64434	1			T25	2		T12	3		T15	204
valid_sources[0x0d]	73987	1			T2	13		T12	8		T15	232
valid_sources[0x0e]	69589	1			T25	4		T2	17		T12	1
valid_sources[0x0f]	74653	1			T2	14		T11	1		T14	9
valid_sources[0x10]	75994	1			T2	3		T14	7		T15	275
valid_sources[0x11]	66107	1			T25	3		T15	212		T18	22
valid_sources[0x12]	65999	1			T2	3		T12	9		T15	246
valid_sources[0x13]	71786	1			T2	47		T12	1		T14	2
valid_sources[0x14]	67613	1			T2	10		T12	6		T15	190
valid_sources[0x15]	64305	1			T25	3		T11	2		T12	1
valid_sources[0x16]	71061	1			T11	1		T12	1		T15	260
valid_sources[0x17]	78351	1			T12	4		T15	219		T18	5
valid_sources[0x18]	64415	1			T25	2		T2	4		T15	230
valid_sources[0x19]	66777	1			T25	4		T2	24		T11	1
valid_sources[0x1a]	75301	1			T25	5		T2	31		T15	277
valid_sources[0x1b]	74314	1			T24	3		T25	1		T2	5
valid_sources[0x1c]	78192	1			T25	1		T2	9		T12	1
valid_sources[0x1d]	72260	1			T15	237		T18	4		T104	4
valid_sources[0x1e]	66145	1			T24	1		T25	2		T2	26
valid_sources[0x1f]	62308	1			T2	33		T12	1		T15	225
valid_sources[0x20]	62819	1			T15	254		T17	38		T18	11
valid_sources[0x21]	63748	1			T25	5		T15	245		T18	6
valid_sources[0x22]	72605	1			T25	3		T2	7		T12	6
valid_sources[0x23]	60584	1			T25	1		T12	1		T15	195
valid_sources[0x24]	63516	1			T24	1		T15	242		T18	9
valid_sources[0x25]	70450	1			T2	4		T12	2		T15	232
valid_sources[0x26]	60016	1			T25	1		T12	5		T15	302
valid_sources[0x27]	63643	1			T25	1		T2	19		T15	236
valid_sources[0x28]	65945	1			T25	2		T12	1		T15	230
valid_sources[0x29]	74211	1			T25	1		T15	294		T18	18
valid_sources[0x2a]	75666	1			T2	5		T12	1		T15	246
valid_sources[0x2b]	68923	1			T25	4		T12	6		T15	348
valid_sources[0x2c]	70430	1			T2	1		T12	3		T15	222
valid_sources[0x2d]	60899	1			T25	2		T12	2		T15	249
valid_sources[0x2e]	109832	1			T2	5		T12	4		T15	258
valid_sources[0x2f]	70937	1			T25	1		T12	1		T15	217
valid_sources[0x30]	66849	1			T25	1		T12	1		T15	237
valid_sources[0x31]	62029	1			T25	1		T2	11		T11	2
valid_sources[0x32]	63813	1			T2	23		T12	1		T15	324
valid_sources[0x33]	69438	1			T12	5		T15	263		T18	21
valid_sources[0x34]	59851	1			T25	2		T2	10		T12	4
valid_sources[0x35]	63428	1			T2	40		T12	3		T15	227
valid_sources[0x36]	207195	1			T2	48		T12	1		T15	222
valid_sources[0x37]	59491	1			T2	28		T14	2		T15	215
valid_sources[0x38]	66913	1			T2	2		T15	267		T18	16
valid_sources[0x39]	70201	1			T15	280		T16	2		T18	20
valid_sources[0x3a]	71058	1			T25	1		T2	10		T15	268
valid_sources[0x3b]	66438	1			T11	1		T12	3		T15	252
valid_sources[0x3c]	59840	1			T2	2		T15	219		T18	8
valid_sources[0x3d]	59435	1			T25	2		T2	4		T14	4
valid_sources[0x3e]	71432	1			T2	11		T15	251		T18	18
valid_sources[0x3f]	56136	1			T25	2		T2	6		T12	5
valid_sources[0x40]	69156	1			T25	1		T15	235		T18	19
valid_sources[0x41]	61009	1			T2	66		T15	248		T16	1
valid_sources[0x42]	63795	1			T25	3		T15	272		T17	16
valid_sources[0x43]	72589	1			T25	1		T2	39		T12	4
valid_sources[0x44]	72897	1			T2	6		T12	4		T15	336
valid_sources[0x45]	66726	1			T25	1		T2	4		T15	206
valid_sources[0x46]	72892	1			T25	1		T2	15		T12	10
valid_sources[0x47]	70318	1			T2	6		T12	1		T15	191
valid_sources[0x48]	57256	1			T25	1		T2	25		T12	1
valid_sources[0x49]	81542	1			T15	243		T16	8		T18	19
valid_sources[0x4a]	74480	1			T2	17		T11	1		T12	2
valid_sources[0x4b]	65127	1			T2	35		T12	1		T14	20
valid_sources[0x4c]	71160	1			T25	3		T2	23		T12	1
valid_sources[0x4d]	66188	1			T11	1		T12	2		T15	216
valid_sources[0x4e]	70419	1			T25	1		T2	2		T12	2
valid_sources[0x4f]	66052	1			T2	5		T12	8		T15	245
valid_sources[0x50]	60455	1			T25	1		T2	17		T15	251
valid_sources[0x51]	207689	1			T25	1		T2	3		T15	249
valid_sources[0x52]	59919	1			T2	32		T12	3		T14	2
valid_sources[0x53]	61760	1			T25	1		T11	1		T12	11
valid_sources[0x54]	76173	1			T11	1		T15	218		T18	9
valid_sources[0x55]	65904	1			T25	1		T2	1		T15	230
valid_sources[0x56]	69647	1			T25	2		T12	6		T15	232
valid_sources[0x57]	67774	1			T2	17		T12	3		T15	249
valid_sources[0x58]	59952	1			T25	2		T15	242		T18	11
valid_sources[0x59]	63275	1			T25	3		T12	2		T15	255
valid_sources[0x5a]	62027	1			T25	1		T12	1		T14	1
valid_sources[0x5b]	64585	1			T12	7		T15	215		T17	11
valid_sources[0x5c]	71951	1			T2	24		T15	257		T16	2
valid_sources[0x5d]	65335	1			T12	6		T15	258		T18	7
valid_sources[0x5e]	67896	1			T25	2		T2	25		T12	4
valid_sources[0x5f]	63182	1			T25	1		T2	30		T15	236
valid_sources[0x60]	66847	1			T25	2		T2	30		T12	1
valid_sources[0x61]	71048	1			T12	3		T15	242		T16	7
valid_sources[0x62]	66799	1			T2	70		T11	1		T12	1
valid_sources[0x63]	66720	1			T25	1		T15	225		T18	22
valid_sources[0x64]	66007	1			T12	1		T15	221		T18	11
valid_sources[0x65]	68815	1			T15	207		T18	29		T105	3
valid_sources[0x66]	63882	1			T2	28		T12	1		T15	228
valid_sources[0x67]	60047	1			T12	1		T15	229		T18	28
valid_sources[0x68]	58121	1			T24	1		T2	9		T12	2
valid_sources[0x69]	70636	1			T25	2		T2	15		T12	1
valid_sources[0x6a]	77501	1			T25	1		T12	4		T15	242
valid_sources[0x6b]	65631	1			T25	4		T12	1		T15	316
valid_sources[0x6c]	73376	1			T2	76		T12	2		T15	263
valid_sources[0x6d]	68468	1			T25	1		T2	25		T14	3
valid_sources[0x6e]	73579	1			T25	2		T12	7		T15	293
valid_sources[0x6f]	78285	1			T11	1		T12	5		T15	204
valid_sources[0x70]	69505	1			T12	5		T15	212		T18	28
valid_sources[0x71]	69567	1			T25	1		T2	37		T12	1
valid_sources[0x72]	64825	1			T25	1		T2	45		T14	1
valid_sources[0x73]	62732	1			T15	240		T18	23		T106	4
valid_sources[0x74]	67054	1			T25	2		T2	24		T15	257
valid_sources[0x75]	67783	1			T25	2		T2	13		T12	4
valid_sources[0x76]	63560	1			T12	2		T15	255		T18	23
valid_sources[0x77]	57715	1			T15	214		T17	8		T18	14
valid_sources[0x78]	70569	1			T12	6		T15	248		T18	9
valid_sources[0x79]	55826	1			T25	3		T2	19		T12	4
valid_sources[0x7a]	66535	1			T25	1		T2	28		T12	2
valid_sources[0x7b]	64339	1			T14	8		T15	266		T18	19
valid_sources[0x7c]	63658	1			T25	1		T2	3		T14	9
valid_sources[0x7d]	80957	1			T25	3		T2	4		T11	1
valid_sources[0x7e]	172027	1			T25	2		T26	245		T2	14
valid_sources[0x7f]	62108	1			T25	3		T2	1		T15	245
valid_sources[0x80]	65385	1			T2	37		T12	4		T15	248

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4209174

1

T25

67

T26

21

T1

18738

values[0x0]

all_enables

biggest_size

5376123

1

T24

2

T25

50

T26

84

values[0x1]

all_enables

biggest_size

5379173

1

T24

2

T25

54

T26

111