Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	144226188	0	0	0
ctrl_en_input_filter_rd_A	144226188	82863	0	0
intr_ctrl_en_falling_rd_A	144226188	84524	0	0
intr_ctrl_en_lvlhigh_rd_A	144226188	83558	0	0
intr_ctrl_en_lvllow_rd_A	144226188	84924	0	0
intr_ctrl_en_rising_rd_A	144226188	83374	0	0
intr_enable_rd_A	144226188	83611	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144226188	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144226188	82863	0	0
T1	123263	3527	0	0
T2	34944	205	0	0
T3	0	3968	0	0
T4	0	157	0	0
T5	0	9	0	0
T6	0	4	0	0
T7	0	282	0	0
T8	0	1778	0	0
T9	0	3239	0	0
T10	0	64	0	0
T11	1390	0	0	0
T12	7441	0	0	0
T13	4172	0	0	0
T14	3984	0	0	0
T15	653491	0	0	0
T16	2367	0	0	0
T17	6115	0	0	0
T18	75191	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144226188	84524	0	0
T1	123263	3344	0	0
T2	34944	237	0	0
T3	0	4257	0	0
T4	0	194	0	0
T7	0	257	0	0
T8	0	2090	0	0
T9	0	3416	0	0
T10	0	103	0	0
T11	1390	0	0	0
T12	7441	0	0	0
T13	4172	0	0	0
T14	3984	0	0	0
T15	653491	0	0	0
T16	2367	0	0	0
T17	6115	0	0	0
T18	75191	0	0	0
T19	0	366	0	0
T20	0	61	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144226188	83558	0	0
T1	123263	3243	0	0
T2	34944	179	0	0
T3	0	4241	0	0
T4	0	167	0	0
T6	0	2	0	0
T7	0	369	0	0
T8	0	2047	0	0
T9	0	3110	0	0
T11	1390	0	0	0
T12	7441	0	0	0
T13	4172	0	0	0
T14	3984	0	0	0
T15	653491	0	0	0
T16	2367	0	0	0
T17	6115	0	0	0
T18	75191	0	0	0
T21	0	2	0	0
T22	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144226188	84924	0	0
T1	123263	3472	0	0
T2	34944	177	0	0
T3	0	3879	0	0
T4	0	140	0	0
T5	0	3	0	0
T7	0	278	0	0
T8	0	1994	0	0
T9	0	3113	0	0
T10	0	86	0	0
T11	1390	0	0	0
T12	7441	0	0	0
T13	4172	0	0	0
T14	3984	0	0	0
T15	653491	0	0	0
T16	2367	0	0	0
T17	6115	0	0	0
T18	75191	0	0	0
T19	0	434	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144226188	83374	0	0
T1	123263	3397	0	0
T2	34944	186	0	0
T3	0	4277	0	0
T4	0	139	0	0
T5	0	8	0	0
T6	0	16	0	0
T7	0	378	0	0
T8	0	1939	0	0
T9	0	3278	0	0
T11	1390	0	0	0
T12	7441	0	0	0
T13	4172	0	0	0
T14	3984	0	0	0
T15	653491	0	0	0
T16	2367	0	0	0
T17	6115	0	0	0
T18	75191	0	0	0
T22	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144226188	83611	0	0
T1	123263	3362	0	0
T2	34944	301	0	0
T3	0	4180	0	0
T4	0	210	0	0
T7	0	238	0	0
T8	0	1906	0	0
T9	0	3366	0	0
T10	0	59	0	0
T11	1390	0	0	0
T12	7441	0	0	0
T13	4172	0	0	0
T14	3984	0	0	0
T15	653491	0	0	0
T16	2367	0	0	0
T17	6115	0	0	0
T18	75191	0	0	0
T19	0	342	0	0
T23	0	4	0	0