Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4566807	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

20703732

1

T33

244

T1

154

T11

1444

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10017931	1			T33	151		T1	18		T11	1728
values[0x0]	7492898	1			T33	86		T1	80		T11	303
values[0x1]	7759710	1			T33	85		T1	64		T11	279

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3502955	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21767584

1

T33

264

T1

158

T11

1628

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	89332	1			T11	4		T12	2		T15	7
valid_sources[0x01]	97468	1			T11	18		T13	10		T15	4
valid_sources[0x02]	92640	1			T33	1		T1	2		T11	19
valid_sources[0x03]	90270	1			T11	3		T12	1		T15	5
valid_sources[0x04]	92111	1			T15	3		T16	3		T18	6
valid_sources[0x05]	223805	1			T1	2		T12	1		T16	1
valid_sources[0x06]	94229	1			T33	10		T1	2		T11	1
valid_sources[0x07]	89937	1			T1	1		T11	4		T12	2
valid_sources[0x08]	93941	1			T33	13		T11	21		T15	1
valid_sources[0x09]	94360	1			T11	15		T12	1		T18	11
valid_sources[0x0a]	92939	1			T11	33		T12	1		T15	3
valid_sources[0x0b]	89746	1			T15	15		T16	4		T18	5
valid_sources[0x0c]	93533	1			T33	1		T1	2		T11	13
valid_sources[0x0d]	91544	1			T33	4		T11	13		T15	1
valid_sources[0x0e]	99318	1			T11	16		T12	1		T13	34
valid_sources[0x0f]	91577	1			T11	1		T12	2		T15	4
valid_sources[0x10]	95546	1			T11	6		T12	1		T15	3
valid_sources[0x11]	96447	1			T11	9		T12	2		T15	10
valid_sources[0x12]	91833	1			T11	8		T16	1		T18	14
valid_sources[0x13]	94903	1			T1	1		T11	8		T12	3
valid_sources[0x14]	94767	1			T11	4		T12	1		T15	5
valid_sources[0x15]	87534	1			T33	3		T1	1		T18	2
valid_sources[0x16]	91589	1			T33	3		T15	1		T16	3
valid_sources[0x17]	92846	1			T33	3		T11	8		T12	2
valid_sources[0x18]	93432	1			T33	2		T11	16		T12	1
valid_sources[0x19]	98318	1			T12	3		T15	6		T18	7
valid_sources[0x1a]	88336	1			T33	1		T11	11		T15	2
valid_sources[0x1b]	96999	1			T33	5		T1	2		T11	1
valid_sources[0x1c]	94030	1			T12	1		T15	8		T18	15
valid_sources[0x1d]	93718	1			T12	2		T15	2		T16	1
valid_sources[0x1e]	93498	1			T33	1		T11	8		T13	9
valid_sources[0x1f]	88227	1			T11	13		T12	1		T15	8
valid_sources[0x20]	95550	1			T1	1		T11	60		T15	8
valid_sources[0x21]	92209	1			T33	2		T12	1		T16	3
valid_sources[0x22]	94012	1			T1	1		T11	27		T12	3
valid_sources[0x23]	90598	1			T33	2		T11	12		T15	4
valid_sources[0x24]	92727	1			T1	5		T11	5		T12	2
valid_sources[0x25]	210626	1			T11	10		T12	2		T15	2
valid_sources[0x26]	89723	1			T11	23		T12	3		T15	3
valid_sources[0x27]	92702	1			T1	1		T11	4		T15	15
valid_sources[0x28]	91866	1			T33	7		T11	11		T15	14
valid_sources[0x29]	103578	1			T11	9		T12	3		T19	4
valid_sources[0x2a]	103534	1			T33	7		T1	2		T15	4
valid_sources[0x2b]	98909	1			T11	6		T15	1		T18	9
valid_sources[0x2c]	88996	1			T33	2		T1	2		T11	5
valid_sources[0x2d]	90611	1			T33	3		T1	1		T12	2
valid_sources[0x2e]	87853	1			T12	6		T15	2		T19	13
valid_sources[0x2f]	114560	1			T11	9		T12	1		T15	4
valid_sources[0x30]	97210	1			T1	1		T12	1		T15	11
valid_sources[0x31]	92404	1			T11	5		T12	1		T15	8
valid_sources[0x32]	87494	1			T33	7		T11	3		T12	2
valid_sources[0x33]	91180	1			T11	9		T12	1		T15	5
valid_sources[0x34]	91162	1			T1	5		T11	5		T15	3
valid_sources[0x35]	91026	1			T33	2		T11	21		T15	9
valid_sources[0x36]	198520	1			T1	1		T12	3		T15	4
valid_sources[0x37]	91270	1			T1	1		T11	1		T18	18
valid_sources[0x38]	91329	1			T1	1		T11	1		T18	4
valid_sources[0x39]	91107	1			T1	2		T11	22		T15	7
valid_sources[0x3a]	92387	1			T1	1		T11	33		T15	6
valid_sources[0x3b]	90808	1			T1	1		T15	7		T19	11
valid_sources[0x3c]	92885	1			T11	11		T15	12		T18	3
valid_sources[0x3d]	91143	1			T11	7		T12	2		T15	2
valid_sources[0x3e]	90674	1			T11	2		T12	1		T18	18
valid_sources[0x3f]	96656	1			T1	2		T11	7		T12	1
valid_sources[0x40]	91215	1			T33	2		T11	2		T15	2
valid_sources[0x41]	103066	1			T33	6		T1	2		T11	12
valid_sources[0x42]	95889	1			T33	1		T11	19		T12	2
valid_sources[0x43]	232852	1			T11	10		T15	8		T16	3
valid_sources[0x44]	91153	1			T11	5		T12	1		T15	4
valid_sources[0x45]	94064	1			T33	1		T1	1		T11	8
valid_sources[0x46]	88777	1			T33	1		T11	7		T15	1
valid_sources[0x47]	151271	1			T11	18		T15	11		T18	1
valid_sources[0x48]	97000	1			T33	3		T1	4		T11	26
valid_sources[0x49]	102242	1			T33	4		T11	1		T12	3
valid_sources[0x4a]	87638	1			T15	6		T18	7		T19	14
valid_sources[0x4b]	99127	1			T11	12		T12	2		T15	4
valid_sources[0x4c]	88720	1			T33	3		T11	1		T15	1
valid_sources[0x4d]	90309	1			T33	6		T11	29		T12	1
valid_sources[0x4e]	219660	1			T33	4		T1	1		T11	11
valid_sources[0x4f]	87628	1			T11	11		T15	9		T18	6
valid_sources[0x50]	90687	1			T33	2		T11	2		T12	1
valid_sources[0x51]	91050	1			T11	2		T12	1		T15	7
valid_sources[0x52]	92791	1			T1	2		T11	1		T15	6
valid_sources[0x53]	95993	1			T33	2		T12	1		T13	27
valid_sources[0x54]	94025	1			T11	10		T15	1		T18	21
valid_sources[0x55]	103815	1			T33	2		T1	2		T11	3
valid_sources[0x56]	89345	1			T11	15		T15	5		T18	2
valid_sources[0x57]	209551	1			T11	43		T12	1		T15	4
valid_sources[0x58]	88144	1			T33	1		T11	12		T12	2
valid_sources[0x59]	86909	1			T33	5		T11	21		T15	7
valid_sources[0x5a]	94177	1			T1	2		T11	10		T15	13
valid_sources[0x5b]	97729	1			T11	18		T12	2		T15	2
valid_sources[0x5c]	87575	1			T11	1		T15	3		T18	40
valid_sources[0x5d]	90137	1			T11	12		T12	1		T18	9
valid_sources[0x5e]	88183	1			T33	1		T12	1		T13	10
valid_sources[0x5f]	89438	1			T33	1		T11	12		T15	13
valid_sources[0x60]	91463	1			T33	4		T11	1		T12	2
valid_sources[0x61]	92453	1			T11	14		T16	4		T17	152
valid_sources[0x62]	89043	1			T11	4		T15	1		T19	7
valid_sources[0x63]	99746	1			T1	1		T15	2		T16	1
valid_sources[0x64]	96382	1			T33	1		T11	2		T12	1
valid_sources[0x65]	93490	1			T11	3		T15	15		T18	1
valid_sources[0x66]	94371	1			T11	22		T15	1		T18	7
valid_sources[0x67]	93731	1			T1	2		T11	2		T15	1
valid_sources[0x68]	91820	1			T1	1		T11	6		T12	3
valid_sources[0x69]	97035	1			T33	3		T1	1		T12	3
valid_sources[0x6a]	98728	1			T11	16		T15	6		T16	1
valid_sources[0x6b]	85698	1			T33	1		T11	21		T12	2
valid_sources[0x6c]	94663	1			T33	1		T1	1		T11	6
valid_sources[0x6d]	87674	1			T11	3		T12	1		T15	1
valid_sources[0x6e]	92031	1			T11	29		T15	3		T18	9
valid_sources[0x6f]	89887	1			T11	3		T12	2		T15	2
valid_sources[0x70]	101503	1			T33	1		T11	16		T15	6
valid_sources[0x71]	100824	1			T11	1		T12	1		T15	1
valid_sources[0x72]	100839	1			T1	1		T11	2		T12	1
valid_sources[0x73]	91884	1			T33	1		T11	31		T16	3
valid_sources[0x74]	95057	1			T12	1		T15	4		T18	10
valid_sources[0x75]	91558	1			T11	8		T12	2		T16	5
valid_sources[0x76]	88025	1			T15	1		T16	1		T18	3
valid_sources[0x77]	94475	1			T1	1		T11	23		T12	1
valid_sources[0x78]	88656	1			T1	3		T15	10		T19	17
valid_sources[0x79]	89904	1			T33	1		T1	2		T11	11
valid_sources[0x7a]	93358	1			T11	6		T15	1		T16	6
valid_sources[0x7b]	87149	1			T11	5		T15	8		T16	1
valid_sources[0x7c]	90529	1			T11	5		T15	2		T18	9
valid_sources[0x7d]	94692	1			T1	1		T11	13		T16	3
valid_sources[0x7e]	234038	1			T33	2		T1	1		T11	16
valid_sources[0x7f]	92559	1			T33	1		T11	24		T12	1
valid_sources[0x80]	98098	1			T1	1		T15	7		T16	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5775600

1

T33

73

T1

10

T11

862

values[0x0]

all_enables

biggest_size

7465652

1

T33

86

T1

80

T11

303

values[0x1]

all_enables

biggest_size

7462480

1

T33

85

T1

64

T11

279