Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	202531283	0	0	0
ctrl_en_input_filter_rd_A	202531283	81672	0	0
intr_ctrl_en_falling_rd_A	202531283	82126	0	0
intr_ctrl_en_lvlhigh_rd_A	202531283	81136	0	0
intr_ctrl_en_lvllow_rd_A	202531283	82127	0	0
intr_ctrl_en_rising_rd_A	202531283	80895	0	0
intr_enable_rd_A	202531283	81038	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	81672	0	0
T1	4921	3	0	0
T2	0	1330	0	0
T3	0	16	0	0
T4	0	5738	0	0
T5	0	274	0	0
T6	0	4	0	0
T7	0	9	0	0
T8	0	5	0	0
T9	0	6663	0	0
T10	0	827	0	0
T11	8515	0	0	0
T12	4270	0	0	0
T13	5697	0	0	0
T14	539750	0	0	0
T15	10930	0	0	0
T16	5472	0	0	0
T17	1547	0	0	0
T18	8909	0	0	0
T19	62824	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	82126	0	0
T2	503245	1196	0	0
T3	0	1	0	0
T4	0	5610	0	0
T5	0	218	0	0
T9	0	6704	0	0
T10	0	802	0	0
T20	0	5175	0	0
T21	0	5324	0	0
T22	0	309	0	0
T23	0	158	0	0
T24	7121	0	0	0
T25	93792	0	0	0
T26	8495	0	0	0
T27	5940	0	0	0
T28	4101	0	0	0
T29	3352	0	0	0
T30	1388	0	0	0
T31	15020	0	0	0
T32	1779	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	81136	0	0
T2	503245	1485	0	0
T4	0	5820	0	0
T5	0	257	0	0
T7	0	18	0	0
T9	0	6408	0	0
T10	0	1004	0	0
T20	0	5515	0	0
T21	0	5568	0	0
T22	0	357	0	0
T23	0	87	0	0
T24	7121	0	0	0
T25	93792	0	0	0
T26	8495	0	0	0
T27	5940	0	0	0
T28	4101	0	0	0
T29	3352	0	0	0
T30	1388	0	0	0
T31	15020	0	0	0
T32	1779	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	82127	0	0
T1	4921	4	0	0
T2	0	1402	0	0
T3	0	15	0	0
T4	0	6031	0	0
T5	0	235	0	0
T7	0	14	0	0
T9	0	6376	0	0
T10	0	696	0	0
T11	8515	0	0	0
T12	4270	0	0	0
T13	5697	0	0	0
T14	539750	0	0	0
T15	10930	0	0	0
T16	5472	0	0	0
T17	1547	0	0	0
T18	8909	0	0	0
T19	62824	0	0	0
T20	0	5512	0	0
T21	0	5438	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	80895	0	0
T1	4921	1	0	0
T2	0	1237	0	0
T4	0	5983	0	0
T5	0	347	0	0
T6	0	2	0	0
T7	0	3	0	0
T9	0	6677	0	0
T10	0	784	0	0
T11	8515	0	0	0
T12	4270	0	0	0
T13	5697	0	0	0
T14	539750	0	0	0
T15	10930	0	0	0
T16	5472	0	0	0
T17	1547	0	0	0
T18	8909	0	0	0
T19	62824	0	0	0
T20	0	5537	0	0
T21	0	4975	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	81038	0	0
T2	503245	1498	0	0
T3	0	4	0	0
T4	0	5561	0	0
T5	0	278	0	0
T7	0	3	0	0
T9	0	6367	0	0
T10	0	723	0	0
T20	0	5514	0	0
T21	0	5725	0	0
T22	0	320	0	0
T24	7121	0	0	0
T25	93792	0	0	0
T26	8495	0	0	0
T27	5940	0	0	0
T28	4101	0	0	0
T29	3352	0	0	0
T30	1388	0	0	0
T31	15020	0	0	0
T32	1779	0	0	0