Unified Coverage Report :: Module :: gpio_reg_top

Module : gpio_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.75	100.00	99.01			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.75	100.00	99.01			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.75	100.00	99.01			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.03	97.69	98.53	100.00		98.95	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_en_input_filter	100.00	100.00	100.00			100.00
u_data_in	67.59	77.78	50.00			75.00
u_direct_oe	100.00	100.00
u_direct_out	100.00	100.00
u_intr_ctrl_en_falling	100.00	100.00	100.00			100.00
u_intr_ctrl_en_lvlhigh	100.00	100.00	100.00			100.00
u_intr_ctrl_en_lvllow	100.00	100.00	100.00			100.00
u_intr_ctrl_en_rising	100.00	100.00	100.00			100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_masked_oe_lower_data	100.00	100.00
u_masked_oe_lower_mask	75.00	75.00
u_masked_oe_upper_data	100.00	100.00
u_masked_oe_upper_mask	75.00	75.00
u_masked_out_lower_data	100.00	100.00
u_masked_out_lower_mask	66.67	66.67
u_masked_out_upper_data	100.00	100.00
u_masked_out_upper_mask	66.67	66.67
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : gpio_reg_top

	Line No.	Total	Covered	Percent
TOTAL		129	129	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
ALWAYS	637	17	17	100.00
CONT_ASSIGN	656	1	1	100.00
ALWAYS	660	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	682	1	1	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	686	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	692	1	1	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	695	1	1	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	711	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	729	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
ALWAYS	742	17	17	100.00
ALWAYS	763	22	22	100.00
CONT_ASSIGN	844	0	0
CONT_ASSIGN	852	1	1	100.00
CONT_ASSIGN	853	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv' or '../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
241	1	1
255	1	1
261	1	1
275	1	1
309	1	1
323	1	1
329	1	1
344	1	1
360	1	1
366	1	1
381	1	1
397	1	1
403	1	1
417	1	1
423	1	1
438	1	1
454	1	1
460	1	1
475	1	1
491	1	1
637	1	1
638	1	1
639	1	1
640	1	1
641	1	1
642	1	1
643	1	1
644	1	1
645	1	1
646	1	1
647	1	1
648	1	1
649	1	1
650	1	1
651	1	1
652	1	1
653	1	1
656	1	1
660	1	1
680	1	1
682	1	1
683	1	1
685	1	1
686	1	1
688	1	1
689	1	1
691	1	1
692	1	1
693	1	1
695	1	1
696	1	1
697	1	1
699	1	1
701	1	1
702	1	1
703	1	1
705	1	1
707	1	1
708	1	1
709	1	1
711	1	1
712	1	1
713	1	1
715	1	1
717	1	1
718	1	1
719	1	1
721	1	1
723	1	1
724	1	1
726	1	1
727	1	1
729	1	1
730	1	1
732	1	1
733	1	1
735	1	1
736	1	1
738	1	1
742	1	1
743	1	1
744	1	1
745	1	1
746	1	1
747	1	1
748	1	1
749	1	1
750	1	1
751	1	1
752	1	1
753	1	1
754	1	1
755	1	1
756	1	1
757	1	1
758	1	1
763	1	1
764	1	1
766	1	1
770	1	1
774	1	1
778	1	1
782	1	1
786	1	1
790	1	1
791	1	1
795	1	1
796	1	1
800	1	1
804	1	1
805	1	1
809	1	1
810	1	1
814	1	1
818	1	1
822	1	1
826	1	1
830	1	1
844		unreachable
852	1	1
853	1	1

---

Cond Coverage for Module : gpio_reg_top

	Total	Covered	Percent
Conditions	203	201	99.01
Logical	203	201	99.01
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Not Covered
1	1	Covered	T33,T1,T11

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T33,T1,T11
0	1	Covered	T42,T43,T44
1	0	Covered	T37,T38,T39

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T33,T1,T11
0	0	1	Covered	T42,T43,T44
0	1	0	Covered	T37,T38,T39
1	0	0	Covered	T42,T43,T44

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T33,T1,T11
0	0	1	Covered	T37,T38,T39
0	1	0	Covered	T34,T35,T36
1	0	0	Not Covered

 LINE       638
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T33,T1,T11

 LINE       639
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T33,T1,T11

 LINE       640
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T1,T13,T14

 LINE       641
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T13,T40,T41

 LINE       642
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_DATA_IN_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T33,T1,T11

 LINE       643
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_DIRECT_OUT_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T1,T12,T13

 LINE       644
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OUT_LOWER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T1,T13,T14

 LINE       645
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OUT_UPPER_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T1,T13,T14

 LINE       646
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_DIRECT_OE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T33,T1,T11

 LINE       647
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OE_LOWER_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T1,T13,T14

 LINE       648
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_MASKED_OE_UPPER_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T1,T13,T14

 LINE       649
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_RISING_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T33,T1,T11

 LINE       650
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_FALLING_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T33,T1,T11

 LINE       651
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T33,T1,T11

 LINE       652
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_INTR_CTRL_EN_LVLLOW_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T33,T1,T11

 LINE       653
 EXPRESSION (reg_addr == gpio_reg_pkg::GPIO_CTRL_EN_INPUT_FILTER_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T1,T11,T13

 LINE       656
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T33,T1,T11
1	Covered	T33,T1,T11

 LINE       656
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T33,T1,T11
0	1	Covered	T33,T1,T11
1	0	Covered	T33,T1,T11

 LINE       660
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T33,T1,T11
1	1	Covered	T34,T35,T36

 LINE       660
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T33,T1,T11
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T1,T13,T14
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T13,T14,T40
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T13,T14,T40
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T13,T14,T40
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T1,T13,T14
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T13,T14,T40
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T1,T13,T14
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T1,T13,T14
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T1,T13,T14
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T13,T14,T40
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T13,T14,T40
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T33,T1,T11
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T13,T40,T41
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T13,T14,T40
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T13,T14,T40
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T33,T1,T11

 LINE       660
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T33,T1,T11
1	1	Covered	T33,T1,T11

 LINE       660
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T33,T1,T11
1	1	Covered	T13,T14,T40

 LINE       660
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T1,T14,T40
1	1	Covered	T13,T14,T40

 LINE       660
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T13,T40,T41
1	1	Covered	T13,T40,T41

 LINE       660
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T33,T1,T11
1	1	Covered	T33,T1,T11

 LINE       660
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T1,T12,T13
1	1	Covered	T13,T14,T40

 LINE       660
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T1,T13,T14
1	1	Covered	T13,T14,T40

 LINE       660
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T1,T13,T14
1	1	Covered	T1,T13,T14

 LINE       660
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T33,T1,T11
1	1	Covered	T1,T13,T14

 LINE       660
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T1,T13,T14
1	1	Covered	T1,T13,T14

 LINE       660
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T1,T13,T14
1	1	Covered	T13,T14,T40

 LINE       660
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T33,T1,T11
1	1	Covered	T1,T13,T14

 LINE       660
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T33,T1,T11
1	1	Covered	T13,T14,T40

 LINE       660
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T33,T1,T11
1	1	Covered	T13,T14,T40

 LINE       660
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T33,T1,T11
1	1	Covered	T13,T14,T40

 LINE       660
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T33,T1,T11
1	0	Covered	T1,T11,T14
1	1	Covered	T1,T13,T14

 LINE       680
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T33,T1,T11
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T33,T1,T14

 LINE       683
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T33,T1,T11
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T33,T1,T11

 LINE       686
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T13,T14
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T1,T14,T34

 LINE       689
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T13,T40,T41
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T45,T46,T47

 LINE       692
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T12,T13
1	1	0	Covered	T37,T38,T48
1	1	1	Covered	T14,T34,T49

 LINE       693
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T12,T13
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T1,T12,T13

 LINE       696
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T13,T14
1	1	0	Covered	T48,T50,T51
1	1	1	Covered	T1,T14,T34

 LINE       697
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T13,T14
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T1,T14,T17

 LINE       702
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T13,T14
1	1	0	Covered	T37,T38,T52
1	1	1	Covered	T1,T14,T34

 LINE       703
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T13,T14
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T1,T14,T17

 LINE       708
 EXPRESSION (addr_hit[8] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T33,T1,T11
1	1	0	Covered	T39,T48,T53
1	1	1	Covered	T1,T14,T34

 LINE       709
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T33,T1,T11
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T33,T1,T11

 LINE       712
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T13,T14
1	1	0	Covered	T38,T39,T52
1	1	1	Covered	T1,T14,T34

 LINE       713
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T13,T14
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T1,T14,T17

 LINE       718
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T13,T14
1	1	0	Covered	T48,T54,T50
1	1	1	Covered	T1,T14,T34

 LINE       719
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T13,T14
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T1,T14,T17

 LINE       724
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T33,T1,T11
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T33,T1,T11

 LINE       727
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T33,T1,T11
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T33,T1,T11

 LINE       730
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T33,T1,T11
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T33,T1,T11

 LINE       733
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T33,T1,T11
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T33,T1,T11

 LINE       736
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T1,T11
1	0	1	Covered	T1,T11,T13
1	1	0	Covered	T34,T35,T36
1	1	1	Covered	T1,T11,T18

---

Branch Coverage for Module : gpio_reg_top

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	656	2	2	100.00
IF	68	3	3	100.00
CASE	764	17	17	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv' or '../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	656	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T1,T11
0	Covered	T33,T1,T11

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T33,T1,T11
0	1	Covered	T42,T43,T44
0	0	Covered	T33,T1,T11

	LineNo.	Expression
-1-:	764	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T33,T1,T11
addr_hit[1]	Covered	T33,T1,T11
addr_hit[2]	Covered	T33,T1,T11
addr_hit[3]	Covered	T33,T1,T11
addr_hit[4]	Covered	T33,T1,T11
addr_hit[5]	Covered	T33,T1,T11
addr_hit[6]	Covered	T33,T1,T11
addr_hit[7]	Covered	T33,T1,T11
addr_hit[8]	Covered	T33,T1,T11
addr_hit[9]	Covered	T33,T1,T11
addr_hit[10]	Covered	T33,T1,T11
addr_hit[11]	Covered	T33,T1,T11
addr_hit[12]	Covered	T33,T1,T11
addr_hit[13]	Covered	T33,T1,T11
addr_hit[14]	Covered	T33,T1,T11
addr_hit[15]	Covered	T33,T1,T11
default	Covered	T33,T1,T11

---

Assert Coverage for Module : gpio_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	202531283	19153748	0	0
reAfterRv	202531283	19153748	0	0
rePulse	202531283	8487506	0	0
wePulse	202531283	10666242	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	19153748	0	0
T1	4921	162	0	0
T11	8515	2310	0	0
T12	4270	226	0	0
T13	5697	423	0	0
T14	539750	92681	0	0
T15	10930	1253	0	0
T16	5472	293	0	0
T17	1547	152	0	0
T18	8909	2373	0	0
T33	5594	322	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	19153748	0	0
T1	4921	162	0	0
T11	8515	2310	0	0
T12	4270	226	0	0
T13	5697	423	0	0
T14	539750	92681	0	0
T15	10930	1253	0	0
T16	5472	293	0	0
T17	1547	152	0	0
T18	8909	2373	0	0
T33	5594	322	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	8487506	0	0
T1	4921	18	0	0
T11	8515	1728	0	0
T12	4270	40	0	0
T13	5697	37	0	0
T14	539750	39934	0	0
T15	10930	545	0	0
T16	5472	108	0	0
T17	1547	25	0	0
T18	8909	1764	0	0
T33	5594	151	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	202531283	10666242	0	0
T1	4921	144	0	0
T11	8515	582	0	0
T12	4270	186	0	0
T13	5697	386	0	0
T14	539750	52747	0	0
T15	10930	708	0	0
T16	5472	185	0	0
T17	1547	127	0	0
T18	8909	609	0	0
T33	5594	171	0	0