Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3732753	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16938076

1

T31

290

T32

69

T33

112

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8188835	1			T31	67		T32	51		T33	18
values[0x0]	6128588	1			T31	120		T32	24		T33	58
values[0x1]	6353406	1			T31	137		T32	22		T33	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2862205	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17808624

1

T31

298

T32

72

T33

116

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	70591	1			T34	2		T13	1		T14	12
valid_sources[0x01]	78463	1			T34	2		T1	5		T14	13
valid_sources[0x02]	78652	1			T32	6		T1	3		T14	7
valid_sources[0x03]	81404	1			T32	1		T34	4		T11	1
valid_sources[0x04]	73884	1			T34	3		T1	1		T13	6
valid_sources[0x05]	75513	1			T32	4		T34	2		T11	7
valid_sources[0x06]	76216	1			T34	4		T1	3		T13	1
valid_sources[0x07]	74647	1			T34	1		T13	1		T14	9
valid_sources[0x08]	84273	1			T34	4		T13	1		T14	13
valid_sources[0x09]	76714	1			T34	2		T1	9		T13	3
valid_sources[0x0a]	78138	1			T34	2		T14	12		T119	12
valid_sources[0x0b]	75386	1			T32	1		T34	3		T1	7
valid_sources[0x0c]	75061	1			T34	3		T1	3		T14	14
valid_sources[0x0d]	79144	1			T34	1		T11	1		T13	5
valid_sources[0x0e]	72096	1			T34	5		T11	5		T14	16
valid_sources[0x0f]	87766	1			T32	2		T34	1		T13	1
valid_sources[0x10]	71256	1			T34	1		T14	13		T119	15
valid_sources[0x11]	76534	1			T34	2		T14	16		T119	11
valid_sources[0x12]	84941	1			T34	1		T13	2		T14	17
valid_sources[0x13]	82221	1			T32	1		T34	6		T1	4
valid_sources[0x14]	77905	1			T34	6		T1	5		T11	2
valid_sources[0x15]	82993	1			T32	4		T34	3		T11	1
valid_sources[0x16]	80459	1			T34	3		T1	6		T11	1
valid_sources[0x17]	88335	1			T34	1		T11	3		T14	17
valid_sources[0x18]	85660	1			T34	1		T13	3		T14	10
valid_sources[0x19]	90233	1			T34	2		T14	17		T119	7
valid_sources[0x1a]	73351	1			T32	1		T34	3		T13	1
valid_sources[0x1b]	79000	1			T32	1		T34	7		T13	1
valid_sources[0x1c]	81370	1			T34	1		T13	3		T14	21
valid_sources[0x1d]	86800	1			T34	1		T14	10		T119	14
valid_sources[0x1e]	118352	1			T32	1		T34	3		T1	3
valid_sources[0x1f]	77755	1			T32	2		T34	7		T13	5
valid_sources[0x20]	74852	1			T34	2		T1	1		T11	23
valid_sources[0x21]	92783	1			T34	3		T13	2		T14	16
valid_sources[0x22]	71335	1			T34	8		T13	3		T14	8
valid_sources[0x23]	185634	1			T34	2		T14	24		T119	23
valid_sources[0x24]	74098	1			T34	2		T14	14		T119	11
valid_sources[0x25]	72402	1			T34	3		T11	2		T14	18
valid_sources[0x26]	78246	1			T34	1		T13	3		T14	8
valid_sources[0x27]	79259	1			T32	4		T34	2		T13	1
valid_sources[0x28]	78704	1			T1	3		T14	17		T119	7
valid_sources[0x29]	82643	1			T34	4		T1	5		T11	5
valid_sources[0x2a]	78190	1			T34	5		T1	3		T14	19
valid_sources[0x2b]	79288	1			T13	2		T14	13		T119	9
valid_sources[0x2c]	75843	1			T34	5		T1	3		T13	2
valid_sources[0x2d]	76789	1			T14	12		T119	4		T120	5
valid_sources[0x2e]	78620	1			T34	4		T1	1		T13	4
valid_sources[0x2f]	79461	1			T32	3		T34	3		T13	1
valid_sources[0x30]	119186	1			T11	4		T14	14		T17	1743
valid_sources[0x31]	84728	1			T34	4		T13	1		T14	18
valid_sources[0x32]	76960	1			T34	2		T11	6		T13	1
valid_sources[0x33]	72523	1			T32	1		T34	3		T13	2
valid_sources[0x34]	81916	1			T34	4		T11	6		T13	4
valid_sources[0x35]	85364	1			T14	14		T119	10		T120	4
valid_sources[0x36]	83335	1			T34	1		T14	19		T119	10
valid_sources[0x37]	82147	1			T34	2		T14	21		T119	13
valid_sources[0x38]	117372	1			T32	1		T34	2		T13	2
valid_sources[0x39]	79641	1			T34	3		T13	1		T14	15
valid_sources[0x3a]	78862	1			T34	1		T13	6		T14	12
valid_sources[0x3b]	90927	1			T32	2		T34	3		T14	11
valid_sources[0x3c]	79608	1			T32	1		T34	3		T14	17
valid_sources[0x3d]	77585	1			T34	2		T13	2		T14	20
valid_sources[0x3e]	73822	1			T34	4		T14	15		T119	11
valid_sources[0x3f]	74128	1			T34	2		T14	20		T119	19
valid_sources[0x40]	72037	1			T32	1		T34	1		T1	2
valid_sources[0x41]	92369	1			T34	1		T14	17		T119	11
valid_sources[0x42]	71851	1			T34	5		T1	2		T13	4
valid_sources[0x43]	75805	1			T34	2		T11	8		T14	13
valid_sources[0x44]	87198	1			T32	2		T34	3		T1	7
valid_sources[0x45]	75743	1			T34	3		T1	3		T14	11
valid_sources[0x46]	80887	1			T14	21		T119	16		T120	10
valid_sources[0x47]	70470	1			T34	5		T14	15		T119	13
valid_sources[0x48]	79285	1			T34	2		T14	12		T119	16
valid_sources[0x49]	79940	1			T34	3		T13	1		T14	14
valid_sources[0x4a]	73972	1			T34	2		T13	5		T14	17
valid_sources[0x4b]	78390	1			T34	2		T11	6		T13	1
valid_sources[0x4c]	76740	1			T34	4		T13	2		T14	14
valid_sources[0x4d]	74733	1			T34	4		T1	1		T13	6
valid_sources[0x4e]	77809	1			T34	2		T14	10		T119	15
valid_sources[0x4f]	80688	1			T34	3		T13	1		T14	13
valid_sources[0x50]	80597	1			T34	5		T1	1		T11	22
valid_sources[0x51]	84504	1			T34	1		T14	13		T119	16
valid_sources[0x52]	76144	1			T34	1		T13	3		T14	13
valid_sources[0x53]	72941	1			T12	3469		T13	1		T14	15
valid_sources[0x54]	69477	1			T32	1		T34	5		T1	2
valid_sources[0x55]	81636	1			T34	3		T13	4		T14	15
valid_sources[0x56]	72603	1			T32	1		T34	4		T11	6
valid_sources[0x57]	85090	1			T34	1		T1	11		T13	8
valid_sources[0x58]	84399	1			T14	9		T119	13		T120	10
valid_sources[0x59]	76108	1			T32	2		T34	1		T11	7
valid_sources[0x5a]	78304	1			T34	2		T13	5		T14	15
valid_sources[0x5b]	84094	1			T34	3		T1	1		T14	16
valid_sources[0x5c]	77888	1			T34	1		T14	13		T119	13
valid_sources[0x5d]	171858	1			T11	1		T14	12		T119	11
valid_sources[0x5e]	71549	1			T34	4		T1	4		T14	15
valid_sources[0x5f]	79125	1			T34	3		T1	5		T13	2
valid_sources[0x60]	163163	1			T34	7		T13	9		T14	7
valid_sources[0x61]	80306	1			T34	7		T1	3		T13	6
valid_sources[0x62]	78686	1			T34	5		T1	8		T14	16
valid_sources[0x63]	74138	1			T32	1		T34	4		T14	23
valid_sources[0x64]	83173	1			T34	3		T13	1		T14	15
valid_sources[0x65]	86978	1			T34	2		T14	15		T119	12
valid_sources[0x66]	88688	1			T34	4		T14	13		T119	16
valid_sources[0x67]	73998	1			T34	1		T1	2		T14	14
valid_sources[0x68]	69403	1			T34	3		T14	11		T119	12
valid_sources[0x69]	76516	1			T34	2		T1	1		T14	15
valid_sources[0x6a]	75902	1			T32	1		T34	2		T13	2
valid_sources[0x6b]	85982	1			T32	1		T34	2		T11	2
valid_sources[0x6c]	80082	1			T34	2		T14	7		T119	19
valid_sources[0x6d]	80164	1			T34	3		T14	13		T19	1
valid_sources[0x6e]	74906	1			T34	2		T1	5		T11	2
valid_sources[0x6f]	79559	1			T34	3		T14	17		T44	1
valid_sources[0x70]	81668	1			T1	6		T14	8		T119	11
valid_sources[0x71]	80273	1			T34	1		T14	10		T119	9
valid_sources[0x72]	73552	1			T32	2		T34	3		T13	1
valid_sources[0x73]	92455	1			T32	1		T11	6		T13	1
valid_sources[0x74]	80372	1			T34	3		T1	1		T14	11
valid_sources[0x75]	77533	1			T34	4		T13	1		T14	13
valid_sources[0x76]	75511	1			T34	4		T1	6		T11	7
valid_sources[0x77]	79702	1			T34	2		T13	1		T14	23
valid_sources[0x78]	77284	1			T1	3		T13	2		T14	19
valid_sources[0x79]	70738	1			T34	3		T1	1		T13	2
valid_sources[0x7a]	85741	1			T34	4		T14	15		T119	14
valid_sources[0x7b]	78413	1			T34	1		T14	22		T119	11
valid_sources[0x7c]	76865	1			T32	1		T34	2		T11	26
valid_sources[0x7d]	72274	1			T34	2		T1	1		T13	1
valid_sources[0x7e]	81554	1			T34	2		T1	2		T13	1
valid_sources[0x7f]	76505	1			T14	15		T19	9		T119	4
valid_sources[0x80]	81719	1			T32	1		T34	1		T13	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4722355

1

T31

33

T32

23

T33

6

values[0x0]

all_enables

biggest_size

6106249

1

T31

120

T32

24

T33

58

values[0x1]

all_enables

biggest_size

6109472

1

T31

137

T32

22

T33

48