Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	177008740	0	0	0
ctrl_en_input_filter_rd_A	177008740	80358	0	0
intr_ctrl_en_falling_rd_A	177008740	83185	0	0
intr_ctrl_en_lvlhigh_rd_A	177008740	80841	0	0
intr_ctrl_en_lvllow_rd_A	177008740	82345	0	0
intr_ctrl_en_rising_rd_A	177008740	81875	0	0
intr_enable_rd_A	177008740	82033	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177008740	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177008740	80358	0	0
T1	8732	7	0	0
T2	0	207	0	0
T3	0	275	0	0
T4	0	849	0	0
T5	0	56	0	0
T6	0	444	0	0
T7	0	255	0	0
T8	0	3385	0	0
T9	0	6611	0	0
T10	0	943	0	0
T11	3120	0	0	0
T12	25987	0	0	0
T13	2579	0	0	0
T14	9658	0	0	0
T15	3694	0	0	0
T16	5855	0	0	0
T17	26187	0	0	0
T18	425482	0	0	0
T19	3068	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177008740	83185	0	0
T1	8732	9	0	0
T2	0	252	0	0
T3	0	317	0	0
T4	0	923	0	0
T5	0	46	0	0
T6	0	632	0	0
T7	0	208	0	0
T8	0	3576	0	0
T11	3120	0	0	0
T12	25987	0	0	0
T13	2579	0	0	0
T14	9658	0	0	0
T15	3694	0	0	0
T16	5855	0	0	0
T17	26187	0	0	0
T18	425482	0	0	0
T19	3068	0	0	0
T20	0	9	0	0
T21	0	5	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177008740	80841	0	0
T2	37698	286	0	0
T3	35264	259	0	0
T4	0	867	0	0
T5	0	66	0	0
T6	0	520	0	0
T7	0	183	0	0
T8	0	3530	0	0
T9	0	6909	0	0
T10	0	1026	0	0
T22	0	8	0	0
T23	9206	0	0	0
T24	124688	0	0	0
T25	2629	0	0	0
T26	825	0	0	0
T27	7542	0	0	0
T28	13770	0	0	0
T29	2648	0	0	0
T30	2004	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177008740	82345	0	0
T2	37698	137	0	0
T3	35264	252	0	0
T4	0	952	0	0
T5	0	85	0	0
T6	0	612	0	0
T7	0	240	0	0
T8	0	3780	0	0
T9	0	6454	0	0
T20	0	4	0	0
T21	0	3	0	0
T23	9206	0	0	0
T24	124688	0	0	0
T25	2629	0	0	0
T26	825	0	0	0
T27	7542	0	0	0
T28	13770	0	0	0
T29	2648	0	0	0
T30	2004	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177008740	81875	0	0
T1	8732	5	0	0
T2	0	295	0	0
T3	0	253	0	0
T4	0	1022	0	0
T5	0	97	0	0
T6	0	487	0	0
T7	0	215	0	0
T8	0	3646	0	0
T9	0	6500	0	0
T11	3120	0	0	0
T12	25987	0	0	0
T13	2579	0	0	0
T14	9658	0	0	0
T15	3694	0	0	0
T16	5855	0	0	0
T17	26187	0	0	0
T18	425482	0	0	0
T19	3068	0	0	0
T20	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177008740	82033	0	0
T2	37698	199	0	0
T3	35264	234	0	0
T4	0	835	0	0
T5	0	56	0	0
T6	0	483	0	0
T7	0	238	0	0
T8	0	3512	0	0
T9	0	6461	0	0
T10	0	1067	0	0
T22	0	4	0	0
T23	9206	0	0	0
T24	124688	0	0	0
T25	2629	0	0	0
T26	825	0	0	0
T27	7542	0	0	0
T28	13770	0	0	0
T29	2648	0	0	0
T30	2004	0	0	0