Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3177859	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13837288

1

T31

452

T32

395

T33

86

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6889254	1			T31	169		T32	459		T33	25
values[0x0]	4982933	1			T31	179		T32	62		T33	39
values[0x1]	5142960	1			T31	181		T32	82		T33	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2452250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14562897

1

T31

472

T32

434

T33

87

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52828	1			T31	5		T32	5		T33	2
valid_sources[0x01]	51131	1			T32	3		T33	2		T34	5
valid_sources[0x02]	60804	1			T31	1		T32	2		T33	1
valid_sources[0x03]	54095	1			T31	4		T32	6		T37	5
valid_sources[0x04]	54449	1			T31	2		T32	1		T33	1
valid_sources[0x05]	54202	1			T34	1		T36	3		T37	2
valid_sources[0x06]	64971	1			T32	2		T34	1		T36	3
valid_sources[0x07]	65495	1			T31	3		T32	3		T34	1
valid_sources[0x08]	55419	1			T31	16		T34	1		T37	2
valid_sources[0x09]	63471	1			T31	1		T32	6		T37	6
valid_sources[0x0a]	58529	1			T32	1		T34	2		T37	1
valid_sources[0x0b]	61870	1			T32	6		T37	3		T40	317
valid_sources[0x0c]	62850	1			T31	10		T32	2		T37	3
valid_sources[0x0d]	56918	1			T31	3		T32	1		T34	4
valid_sources[0x0e]	66775	1			T31	3		T34	3		T37	5
valid_sources[0x0f]	55560	1			T31	2		T37	5		T40	231
valid_sources[0x10]	57227	1			T31	1		T32	2		T36	7
valid_sources[0x11]	61458	1			T32	3		T34	2		T36	1
valid_sources[0x12]	66411	1			T34	6		T37	4		T40	197
valid_sources[0x13]	51565	1			T32	5		T33	1		T36	6
valid_sources[0x14]	51322	1			T31	5		T32	5		T33	1
valid_sources[0x15]	64954	1			T34	5		T37	5		T40	239
valid_sources[0x16]	60111	1			T32	6		T33	1		T34	1
valid_sources[0x17]	59836	1			T31	2		T32	1		T33	1
valid_sources[0x18]	66577	1			T32	1		T34	3		T40	189
valid_sources[0x19]	72046	1			T32	5		T37	4		T40	169
valid_sources[0x1a]	63086	1			T31	9		T33	1		T34	5
valid_sources[0x1b]	63500	1			T34	5		T40	169		T113	4
valid_sources[0x1c]	63436	1			T31	1		T34	3		T37	5
valid_sources[0x1d]	54998	1			T34	1		T37	4		T40	239
valid_sources[0x1e]	58162	1			T31	1		T32	6		T34	5
valid_sources[0x1f]	56573	1			T31	3		T34	1		T36	5
valid_sources[0x20]	57285	1			T31	2		T32	11		T37	4
valid_sources[0x21]	54164	1			T34	1		T37	2		T40	206
valid_sources[0x22]	65800	1			T31	7		T37	3		T40	232
valid_sources[0x23]	62827	1			T31	1		T34	3		T36	2
valid_sources[0x24]	52878	1			T31	2		T32	4		T33	2
valid_sources[0x25]	62247	1			T31	5		T32	2		T34	4
valid_sources[0x26]	55666	1			T31	3		T33	1		T34	3
valid_sources[0x27]	50814	1			T32	5		T37	9		T40	120
valid_sources[0x28]	58341	1			T34	3		T36	1		T37	3
valid_sources[0x29]	205420	1			T34	3		T36	1		T37	1
valid_sources[0x2a]	57753	1			T31	1		T32	1		T36	7
valid_sources[0x2b]	188260	1			T33	2		T34	2		T37	2
valid_sources[0x2c]	65519	1			T32	6		T34	1		T37	3
valid_sources[0x2d]	66366	1			T32	2		T34	2		T37	4
valid_sources[0x2e]	59490	1			T32	4		T34	2		T37	8
valid_sources[0x2f]	58372	1			T37	5		T40	207		T114	2
valid_sources[0x30]	60209	1			T32	2		T34	1		T37	4
valid_sources[0x31]	50786	1			T32	6		T33	1		T40	227
valid_sources[0x32]	56598	1			T31	1		T32	4		T33	1
valid_sources[0x33]	63736	1			T31	4		T32	3		T34	2
valid_sources[0x34]	64821	1			T31	14		T32	5		T37	1
valid_sources[0x35]	65632	1			T31	3		T32	3		T37	6
valid_sources[0x36]	56325	1			T31	2		T32	3		T34	3
valid_sources[0x37]	59053	1			T32	5		T33	1		T34	1
valid_sources[0x38]	57384	1			T31	1		T32	4		T33	2
valid_sources[0x39]	58279	1			T31	1		T32	3		T34	8
valid_sources[0x3a]	83049	1			T37	4		T40	193		T114	2
valid_sources[0x3b]	58626	1			T31	1		T37	2		T40	161
valid_sources[0x3c]	59309	1			T31	3		T32	6		T34	1
valid_sources[0x3d]	63332	1			T31	2		T32	3		T34	2
valid_sources[0x3e]	56565	1			T31	5		T32	2		T37	5
valid_sources[0x3f]	64318	1			T32	3		T33	2		T37	1
valid_sources[0x40]	54802	1			T32	3		T34	2		T40	140
valid_sources[0x41]	144242	1			T31	3		T32	1		T34	2
valid_sources[0x42]	74965	1			T32	6		T37	7		T39	4503
valid_sources[0x43]	59296	1			T31	6		T32	1		T34	1
valid_sources[0x44]	62622	1			T31	2		T32	2		T34	4
valid_sources[0x45]	73647	1			T34	4		T37	2		T40	189
valid_sources[0x46]	59681	1			T32	3		T37	6		T40	384
valid_sources[0x47]	59955	1			T32	1		T33	1		T36	3
valid_sources[0x48]	59105	1			T32	1		T33	1		T34	1
valid_sources[0x49]	59669	1			T31	2		T33	1		T34	5
valid_sources[0x4a]	54791	1			T32	1		T34	6		T37	5
valid_sources[0x4b]	54340	1			T31	2		T33	1		T34	2
valid_sources[0x4c]	108100	1			T32	3		T33	1		T37	5
valid_sources[0x4d]	72023	1			T31	2		T32	8		T33	1
valid_sources[0x4e]	58326	1			T32	7		T34	2		T37	2
valid_sources[0x4f]	59590	1			T31	8		T34	3		T37	3
valid_sources[0x50]	53539	1			T37	1		T40	264		T114	4
valid_sources[0x51]	64719	1			T31	15		T34	1		T36	2
valid_sources[0x52]	59399	1			T31	18		T32	1		T33	2
valid_sources[0x53]	61539	1			T31	1		T37	5		T40	117
valid_sources[0x54]	191319	1			T31	5		T32	4		T33	2
valid_sources[0x55]	196713	1			T31	7		T32	3		T36	7
valid_sources[0x56]	57380	1			T32	2		T33	1		T34	2
valid_sources[0x57]	55087	1			T31	3		T33	1		T37	5
valid_sources[0x58]	85560	1			T31	1		T32	7		T33	1
valid_sources[0x59]	55410	1			T31	7		T33	2		T34	2
valid_sources[0x5a]	59342	1			T32	3		T37	1		T40	261
valid_sources[0x5b]	57254	1			T32	1		T33	2		T34	2
valid_sources[0x5c]	50610	1			T31	3		T32	5		T34	1
valid_sources[0x5d]	60146	1			T31	14		T32	2		T33	1
valid_sources[0x5e]	61200	1			T31	1		T34	1		T37	2
valid_sources[0x5f]	56776	1			T33	2		T34	2		T37	2
valid_sources[0x60]	58158	1			T31	4		T32	2		T33	1
valid_sources[0x61]	53595	1			T32	2		T33	1		T36	2
valid_sources[0x62]	57454	1			T32	4		T34	3		T37	3
valid_sources[0x63]	57497	1			T34	2		T37	1		T40	320
valid_sources[0x64]	71208	1			T31	1		T32	2		T33	1
valid_sources[0x65]	59173	1			T32	8		T34	1		T37	2
valid_sources[0x66]	53168	1			T31	9		T32	3		T33	1
valid_sources[0x67]	64216	1			T34	2		T37	7		T40	265
valid_sources[0x68]	189326	1			T31	2		T32	5		T34	3
valid_sources[0x69]	54900	1			T37	7		T40	167		T113	2
valid_sources[0x6a]	65199	1			T32	1		T33	1		T34	4
valid_sources[0x6b]	52045	1			T32	1		T34	5		T37	3
valid_sources[0x6c]	55499	1			T31	2		T32	1		T34	1
valid_sources[0x6d]	64955	1			T32	2		T34	2		T40	137
valid_sources[0x6e]	57712	1			T32	7		T34	1		T36	1
valid_sources[0x6f]	56711	1			T32	5		T37	4		T40	137
valid_sources[0x70]	66753	1			T31	6		T32	4		T34	3
valid_sources[0x71]	145993	1			T31	7		T32	1		T33	2
valid_sources[0x72]	62248	1			T31	1		T34	5		T37	3
valid_sources[0x73]	59712	1			T32	2		T37	2		T38	303
valid_sources[0x74]	61383	1			T33	1		T36	1		T37	1
valid_sources[0x75]	56487	1			T31	6		T32	2		T37	1
valid_sources[0x76]	63385	1			T31	11		T32	2		T33	2
valid_sources[0x77]	61046	1			T32	2		T33	1		T36	2
valid_sources[0x78]	62762	1			T31	2		T32	2		T33	1
valid_sources[0x79]	58716	1			T31	1		T32	1		T34	1
valid_sources[0x7a]	64603	1			T31	1		T32	1		T33	2
valid_sources[0x7b]	52939	1			T31	1		T32	3		T33	1
valid_sources[0x7c]	54263	1			T31	1		T32	1		T34	1
valid_sources[0x7d]	59698	1			T31	7		T37	4		T40	230
valid_sources[0x7e]	57397	1			T31	4		T32	2		T34	1
valid_sources[0x7f]	51423	1			T31	4		T32	1		T37	1
valid_sources[0x80]	56098	1			T31	4		T32	2		T36	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3906987

1

T31

92

T32

251

T33

11

values[0x0]

all_enables

biggest_size

4966352

1

T31

179

T32

62

T33

39

values[0x1]

all_enables

biggest_size

4963949

1

T31

181

T32

82

T33

36