Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	136344125	0	0	0
ctrl_en_input_filter_rd_A	136344125	40934	0	0
intr_ctrl_en_falling_rd_A	136344125	42250	0	0
intr_ctrl_en_lvlhigh_rd_A	136344125	41258	0	0
intr_ctrl_en_lvllow_rd_A	136344125	42720	0	0
intr_ctrl_en_rising_rd_A	136344125	41777	0	0
intr_enable_rd_A	136344125	42079	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136344125	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136344125	40934	0	0
T1	8538	4	0	0
T2	0	300	0	0
T3	0	1001	0	0
T4	0	6	0	0
T5	0	303	0	0
T6	0	2299	0	0
T7	0	244	0	0
T8	0	13606	0	0
T9	0	6	0	0
T10	0	175	0	0
T11	844	0	0	0
T12	12904	0	0	0
T13	23137	0	0	0
T14	7328	0	0	0
T15	3072	0	0	0
T16	2593	0	0	0
T17	36482	0	0	0
T18	35010	0	0	0
T19	3620	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136344125	42250	0	0
T2	37140	308	0	0
T3	0	973	0	0
T4	0	6	0	0
T5	0	200	0	0
T6	0	2152	0	0
T7	0	268	0	0
T8	0	14901	0	0
T10	0	86	0	0
T20	0	54	0	0
T21	0	3709	0	0
T22	147240	0	0	0
T23	1993	0	0	0
T24	1551	0	0	0
T25	3196	0	0	0
T26	5151	0	0	0
T27	1043	0	0	0
T28	232795	0	0	0
T29	3262	0	0	0
T30	4592	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136344125	41258	0	0
T2	37140	321	0	0
T3	0	1032	0	0
T5	0	181	0	0
T6	0	2094	0	0
T7	0	285	0	0
T8	0	13517	0	0
T9	0	7	0	0
T10	0	134	0	0
T20	0	30	0	0
T21	0	3819	0	0
T22	147240	0	0	0
T23	1993	0	0	0
T24	1551	0	0	0
T25	3196	0	0	0
T26	5151	0	0	0
T27	1043	0	0	0
T28	232795	0	0	0
T29	3262	0	0	0
T30	4592	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136344125	42720	0	0
T2	37140	245	0	0
T3	0	1050	0	0
T4	0	5	0	0
T5	0	254	0	0
T6	0	2393	0	0
T7	0	206	0	0
T8	0	14554	0	0
T9	0	1	0	0
T10	0	109	0	0
T20	0	29	0	0
T22	147240	0	0	0
T23	1993	0	0	0
T24	1551	0	0	0
T25	3196	0	0	0
T26	5151	0	0	0
T27	1043	0	0	0
T28	232795	0	0	0
T29	3262	0	0	0
T30	4592	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136344125	41777	0	0
T2	37140	219	0	0
T3	0	952	0	0
T4	0	4	0	0
T5	0	172	0	0
T6	0	2226	0	0
T7	0	315	0	0
T8	0	14221	0	0
T9	0	3	0	0
T10	0	88	0	0
T20	0	17	0	0
T22	147240	0	0	0
T23	1993	0	0	0
T24	1551	0	0	0
T25	3196	0	0	0
T26	5151	0	0	0
T27	1043	0	0	0
T28	232795	0	0	0
T29	3262	0	0	0
T30	4592	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136344125	42079	0	0
T2	37140	254	0	0
T3	0	1102	0	0
T5	0	279	0	0
T6	0	2307	0	0
T7	0	263	0	0
T8	0	13417	0	0
T9	0	10	0	0
T10	0	111	0	0
T20	0	43	0	0
T21	0	4043	0	0
T22	147240	0	0	0
T23	1993	0	0	0
T24	1551	0	0	0
T25	3196	0	0	0
T26	5151	0	0	0
T27	1043	0	0	0
T28	232795	0	0	0
T29	3262	0	0	0
T30	4592	0	0	0