Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	191318605	0	0	0
ctrl_en_input_filter_rd_A	191318605	46273	0	0
intr_ctrl_en_falling_rd_A	191318605	47281	0	0
intr_ctrl_en_lvlhigh_rd_A	191318605	47032	0	0
intr_ctrl_en_lvllow_rd_A	191318605	47791	0	0
intr_ctrl_en_rising_rd_A	191318605	46193	0	0
intr_enable_rd_A	191318605	46921	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191318605	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191318605	46273	0	0
T1	502033	12333	0	0
T2	0	1791	0	0
T3	0	179	0	0
T4	0	304	0	0
T5	0	228	0	0
T6	0	276	0	0
T7	0	1107	0	0
T8	0	1	0	0
T9	0	1253	0	0
T10	0	6	0	0
T11	4267	0	0	0
T12	3079	0	0	0
T13	2095	0	0	0
T14	359094	0	0	0
T15	4072	0	0	0
T16	37515	0	0	0
T17	2946	0	0	0
T18	2498	0	0	0
T19	5777	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191318605	47281	0	0
T1	502033	12738	0	0
T2	0	1931	0	0
T3	0	103	0	0
T4	0	200	0	0
T5	0	206	0	0
T6	0	318	0	0
T7	0	1190	0	0
T8	0	8	0	0
T9	0	1136	0	0
T10	0	2	0	0
T11	4267	0	0	0
T12	3079	0	0	0
T13	2095	0	0	0
T14	359094	0	0	0
T15	4072	0	0	0
T16	37515	0	0	0
T17	2946	0	0	0
T18	2498	0	0	0
T19	5777	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191318605	47032	0	0
T1	502033	12289	0	0
T2	0	2050	0	0
T3	0	139	0	0
T4	0	280	0	0
T5	0	238	0	0
T6	0	265	0	0
T7	0	1153	0	0
T9	0	1174	0	0
T10	0	2	0	0
T11	4267	0	0	0
T12	3079	0	0	0
T13	2095	0	0	0
T14	359094	0	0	0
T15	4072	0	0	0
T16	37515	0	0	0
T17	2946	0	0	0
T18	2498	0	0	0
T19	5777	0	0	0
T20	0	6	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191318605	47791	0	0
T1	502033	13224	0	0
T2	0	1772	0	0
T3	0	172	0	0
T4	0	283	0	0
T5	0	180	0	0
T6	0	279	0	0
T7	0	1086	0	0
T9	0	1201	0	0
T10	0	10	0	0
T11	4267	0	0	0
T12	3079	0	0	0
T13	2095	0	0	0
T14	359094	0	0	0
T15	4072	0	0	0
T16	37515	0	0	0
T17	2946	0	0	0
T18	2498	0	0	0
T19	5777	0	0	0
T20	0	6	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191318605	46193	0	0
T1	502033	11758	0	0
T2	0	1869	0	0
T3	0	131	0	0
T4	0	251	0	0
T5	0	176	0	0
T6	0	320	0	0
T7	0	1136	0	0
T9	0	1113	0	0
T10	0	6	0	0
T11	4267	0	0	0
T12	3079	0	0	0
T13	2095	0	0	0
T14	359094	0	0	0
T15	4072	0	0	0
T16	37515	0	0	0
T17	2946	0	0	0
T18	2498	0	0	0
T19	5777	0	0	0
T21	0	5557	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191318605	46921	0	0
T1	502033	11821	0	0
T2	0	1927	0	0
T3	0	164	0	0
T4	0	221	0	0
T5	0	297	0	0
T6	0	303	0	0
T7	0	1178	0	0
T9	0	1316	0	0
T11	4267	0	0	0
T12	3079	0	0	0
T13	2095	0	0	0
T14	359094	0	0	0
T15	4072	0	0	0
T16	37515	0	0	0
T17	2946	0	0	0
T18	2498	0	0	0
T19	5777	0	0	0
T20	0	3	0	0
T21	0	5465	0	0