Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	169939781	0	0	0
ctrl_en_input_filter_rd_A	169939781	67800	0	0
intr_ctrl_en_falling_rd_A	169939781	67524	0	0
intr_ctrl_en_lvlhigh_rd_A	169939781	67923	0	0
intr_ctrl_en_lvllow_rd_A	169939781	68985	0	0
intr_ctrl_en_rising_rd_A	169939781	68194	0	0
intr_enable_rd_A	169939781	67648	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169939781	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169939781	67800	0	0
T1	180691	4527	0	0
T2	0	459	0	0
T3	0	9	0	0
T4	0	2588	0	0
T5	0	267	0	0
T6	0	428	0	0
T7	0	8	0	0
T8	0	173	0	0
T9	0	2714	0	0
T10	0	2902	0	0
T11	2842	0	0	0
T12	590015	0	0	0
T13	6831	0	0	0
T14	164751	0	0	0
T15	226248	0	0	0
T16	7125	0	0	0
T17	3849	0	0	0
T18	2769	0	0	0
T19	6817	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169939781	67524	0	0
T1	180691	4495	0	0
T2	0	464	0	0
T4	0	2537	0	0
T5	0	281	0	0
T6	0	483	0	0
T7	0	5	0	0
T8	0	226	0	0
T9	0	2528	0	0
T10	0	2664	0	0
T11	2842	0	0	0
T12	590015	0	0	0
T13	6831	0	0	0
T14	164751	0	0	0
T15	226248	0	0	0
T16	7125	0	0	0
T17	3849	0	0	0
T18	2769	0	0	0
T19	6817	0	0	0
T20	0	151	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169939781	67923	0	0
T1	180691	4482	0	0
T2	0	437	0	0
T3	0	5	0	0
T4	0	2833	0	0
T5	0	288	0	0
T6	0	404	0	0
T8	0	176	0	0
T9	0	2931	0	0
T10	0	2763	0	0
T11	2842	0	0	0
T12	590015	0	0	0
T13	6831	0	0	0
T14	164751	0	0	0
T15	226248	0	0	0
T16	7125	0	0	0
T17	3849	0	0	0
T18	2769	0	0	0
T19	6817	0	0	0
T21	0	7	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169939781	68985	0	0
T1	180691	4311	0	0
T2	0	524	0	0
T3	0	6	0	0
T4	0	2600	0	0
T5	0	292	0	0
T6	0	460	0	0
T7	0	5	0	0
T8	0	197	0	0
T9	0	2787	0	0
T11	2842	0	0	0
T12	590015	0	0	0
T13	6831	0	0	0
T14	164751	0	0	0
T15	226248	0	0	0
T16	7125	0	0	0
T17	3849	0	0	0
T18	2769	0	0	0
T19	6817	0	0	0
T21	0	11	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169939781	68194	0	0
T1	180691	4495	0	0
T2	0	407	0	0
T3	0	9	0	0
T4	0	2553	0	0
T5	0	324	0	0
T6	0	578	0	0
T8	0	186	0	0
T9	0	2669	0	0
T10	0	2768	0	0
T11	2842	0	0	0
T12	590015	0	0	0
T13	6831	0	0	0
T14	164751	0	0	0
T15	226248	0	0	0
T16	7125	0	0	0
T17	3849	0	0	0
T18	2769	0	0	0
T19	6817	0	0	0
T20	0	156	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169939781	67648	0	0
T1	180691	4431	0	0
T2	0	430	0	0
T4	0	2492	0	0
T5	0	228	0	0
T6	0	507	0	0
T7	0	4	0	0
T8	0	181	0	0
T9	0	2802	0	0
T10	0	2758	0	0
T11	2842	0	0	0
T12	590015	0	0	0
T13	6831	0	0	0
T14	164751	0	0	0
T15	226248	0	0	0
T16	7125	0	0	0
T17	3849	0	0	0
T18	2769	0	0	0
T19	6817	0	0	0
T22	0	7	0	0