Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	202839942	0	0	0
ctrl_en_input_filter_rd_A	202839942	49506	0	0
intr_ctrl_en_falling_rd_A	202839942	50543	0	0
intr_ctrl_en_lvlhigh_rd_A	202839942	50324	0	0
intr_ctrl_en_lvllow_rd_A	202839942	50794	0	0
intr_ctrl_en_rising_rd_A	202839942	50569	0	0
intr_enable_rd_A	202839942	50535	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202839942	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202839942	49506	0	0
T1	56304	418	0	0
T2	0	333	0	0
T3	0	5397	0	0
T4	0	158	0	0
T5	0	2	0	0
T6	0	5	0	0
T7	0	150	0	0
T8	0	4122	0	0
T9	0	4183	0	0
T10	0	1438	0	0
T11	6009	0	0	0
T12	534704	0	0	0
T13	505083	0	0	0
T14	1429	0	0	0
T15	45683	0	0	0
T16	6291	0	0	0
T17	3509	0	0	0
T18	2202	0	0	0
T19	3651	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202839942	50543	0	0
T1	56304	452	0	0
T2	0	371	0	0
T3	0	5604	0	0
T4	0	144	0	0
T7	0	241	0	0
T8	0	3889	0	0
T9	0	4434	0	0
T10	0	1458	0	0
T11	6009	0	0	0
T12	534704	0	0	0
T13	505083	0	0	0
T14	1429	0	0	0
T15	45683	0	0	0
T16	6291	0	0	0
T17	3509	0	0	0
T18	2202	0	0	0
T19	3651	0	0	0
T20	0	168	0	0
T21	0	2894	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202839942	50324	0	0
T1	56304	317	0	0
T2	0	301	0	0
T3	0	5959	0	0
T4	0	151	0	0
T5	0	10	0	0
T6	0	5	0	0
T7	0	172	0	0
T8	0	4016	0	0
T9	0	4166	0	0
T10	0	1389	0	0
T11	6009	0	0	0
T12	534704	0	0	0
T13	505083	0	0	0
T14	1429	0	0	0
T15	45683	0	0	0
T16	6291	0	0	0
T17	3509	0	0	0
T18	2202	0	0	0
T19	3651	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202839942	50794	0	0
T1	56304	455	0	0
T2	0	419	0	0
T3	0	5533	0	0
T4	0	129	0	0
T7	0	171	0	0
T8	0	3817	0	0
T9	0	3951	0	0
T10	0	1446	0	0
T11	6009	0	0	0
T12	534704	0	0	0
T13	505083	0	0	0
T14	1429	0	0	0
T15	45683	0	0	0
T16	6291	0	0	0
T17	3509	0	0	0
T18	2202	0	0	0
T19	3651	0	0	0
T20	0	234	0	0
T21	0	3007	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202839942	50569	0	0
T1	56304	357	0	0
T2	0	325	0	0
T3	0	5444	0	0
T4	0	152	0	0
T5	0	5	0	0
T7	0	234	0	0
T8	0	3766	0	0
T9	0	4264	0	0
T10	0	1368	0	0
T11	6009	0	0	0
T12	534704	0	0	0
T13	505083	0	0	0
T14	1429	0	0	0
T15	45683	0	0	0
T16	6291	0	0	0
T17	3509	0	0	0
T18	2202	0	0	0
T19	3651	0	0	0
T20	0	241	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202839942	50535	0	0
T1	56304	476	0	0
T2	0	332	0	0
T3	0	5494	0	0
T4	0	182	0	0
T6	0	12	0	0
T7	0	236	0	0
T8	0	3921	0	0
T9	0	3945	0	0
T10	0	1587	0	0
T11	6009	0	0	0
T12	534704	0	0	0
T13	505083	0	0	0
T14	1429	0	0	0
T15	45683	0	0	0
T16	6291	0	0	0
T17	3509	0	0	0
T18	2202	0	0	0
T19	3651	0	0	0
T20	0	216	0	0