Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4652112	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

20955416

1

T22

353

T23

993

T24

506

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10196008	1			T22	137		T23	1170		T24	271
values[0x0]	7571511	1			T22	146		T23	186		T24	185
values[0x1]	7840009	1			T22	142		T23	186		T24	180

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3571874	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22035654

1

T22

371

T23

1103

T24

526

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	150370	1			T26	1		T29	29		T11	15
valid_sources[0x01]	102299	1			T26	1		T27	5		T11	11
valid_sources[0x02]	94668	1			T22	1		T26	1		T27	3
valid_sources[0x03]	99184	1			T22	4		T26	2		T27	6
valid_sources[0x04]	102020	1			T22	1		T29	18		T11	24
valid_sources[0x05]	93705	1			T29	19		T11	19		T15	185
valid_sources[0x06]	91816	1			T22	2		T29	60		T11	16
valid_sources[0x07]	90204	1			T22	3		T11	24		T15	204
valid_sources[0x08]	101869	1			T22	1		T29	57		T11	13
valid_sources[0x09]	95669	1			T22	2		T11	40		T14	1
valid_sources[0x0a]	95202	1			T22	3		T25	1		T27	5
valid_sources[0x0b]	96045	1			T22	3		T11	22		T15	184
valid_sources[0x0c]	105115	1			T22	3		T25	1		T27	3
valid_sources[0x0d]	90028	1			T22	3		T25	2		T11	19
valid_sources[0x0e]	88229	1			T22	1		T26	2		T11	9
valid_sources[0x0f]	93064	1			T22	1		T26	1		T29	22
valid_sources[0x10]	93315	1			T22	4		T26	1		T11	6
valid_sources[0x11]	96498	1			T25	4		T26	8		T11	9
valid_sources[0x12]	101939	1			T22	3		T27	7		T11	20
valid_sources[0x13]	95619	1			T22	2		T11	24		T15	208
valid_sources[0x14]	97629	1			T25	2		T11	8		T14	9
valid_sources[0x15]	97017	1			T22	3		T11	14		T15	175
valid_sources[0x16]	94620	1			T22	2		T11	26		T15	166
valid_sources[0x17]	93203	1			T22	1		T26	2		T27	10
valid_sources[0x18]	91999	1			T22	4		T26	1		T29	33
valid_sources[0x19]	100173	1			T22	1		T25	4		T26	2
valid_sources[0x1a]	111986	1			T22	3		T25	3		T11	17
valid_sources[0x1b]	87833	1			T22	1		T26	1		T27	1
valid_sources[0x1c]	98065	1			T22	1		T29	49		T11	29
valid_sources[0x1d]	104169	1			T22	1		T29	29		T11	29
valid_sources[0x1e]	90230	1			T22	2		T25	5		T26	1
valid_sources[0x1f]	96240	1			T26	1		T11	8		T15	185
valid_sources[0x20]	96996	1			T22	1		T26	3		T11	4
valid_sources[0x21]	109407	1			T22	1		T29	7		T11	17
valid_sources[0x22]	102663	1			T22	3		T11	9		T15	239
valid_sources[0x23]	94058	1			T22	2		T26	5		T27	1
valid_sources[0x24]	93652	1			T22	1		T26	2		T11	26
valid_sources[0x25]	92296	1			T22	2		T26	1		T29	29
valid_sources[0x26]	95048	1			T22	1		T25	3		T29	3
valid_sources[0x27]	93109	1			T22	3		T27	9		T29	25
valid_sources[0x28]	86086	1			T22	3		T26	1		T11	24
valid_sources[0x29]	105417	1			T22	1		T26	1		T11	24
valid_sources[0x2a]	94786	1			T26	1		T29	16		T11	14
valid_sources[0x2b]	88555	1			T22	5		T27	1		T11	15
valid_sources[0x2c]	99505	1			T22	1		T26	3		T11	15
valid_sources[0x2d]	97349	1			T27	4		T11	23		T15	241
valid_sources[0x2e]	98598	1			T22	2		T26	2		T11	7
valid_sources[0x2f]	93950	1			T22	1		T25	8		T11	18
valid_sources[0x30]	96091	1			T27	12		T29	2		T11	25
valid_sources[0x31]	95405	1			T22	2		T26	1		T29	16
valid_sources[0x32]	91623	1			T22	1		T27	5		T11	5
valid_sources[0x33]	110482	1			T22	1		T26	1		T27	1
valid_sources[0x34]	93888	1			T26	2		T29	36		T11	12
valid_sources[0x35]	101439	1			T22	2		T29	3		T11	10
valid_sources[0x36]	91311	1			T22	4		T25	11		T27	1
valid_sources[0x37]	92399	1			T22	3		T26	2		T29	65
valid_sources[0x38]	102757	1			T25	12		T26	1		T27	8
valid_sources[0x39]	91841	1			T22	3		T29	63		T11	13
valid_sources[0x3a]	92827	1			T22	4		T27	4		T29	2
valid_sources[0x3b]	93099	1			T11	23		T15	192		T17	5
valid_sources[0x3c]	104294	1			T22	1		T26	3		T27	18
valid_sources[0x3d]	94213	1			T26	4		T11	23		T15	204
valid_sources[0x3e]	95739	1			T22	2		T26	1		T27	3
valid_sources[0x3f]	90757	1			T22	1		T26	2		T27	3
valid_sources[0x40]	92963	1			T22	2		T27	1		T11	12
valid_sources[0x41]	92607	1			T22	1		T26	3		T11	5
valid_sources[0x42]	98456	1			T25	11		T29	32		T11	17
valid_sources[0x43]	100029	1			T22	2		T26	1		T27	4
valid_sources[0x44]	95381	1			T25	3		T26	1		T29	59
valid_sources[0x45]	84758	1			T22	1		T27	4		T11	17
valid_sources[0x46]	95355	1			T26	2		T11	3		T15	213
valid_sources[0x47]	101062	1			T22	4		T25	2		T27	4
valid_sources[0x48]	94212	1			T22	2		T11	13		T15	208
valid_sources[0x49]	105230	1			T22	4		T11	12		T15	210
valid_sources[0x4a]	96159	1			T27	12		T11	32		T15	197
valid_sources[0x4b]	107846	1			T22	2		T27	6		T29	3
valid_sources[0x4c]	119799	1			T11	18		T15	180		T17	6
valid_sources[0x4d]	100884	1			T25	1		T26	1		T11	23
valid_sources[0x4e]	99809	1			T22	3		T26	3		T27	2
valid_sources[0x4f]	92861	1			T22	2		T27	6		T28	2
valid_sources[0x50]	138983	1			T25	12		T29	6		T11	25
valid_sources[0x51]	91046	1			T22	2		T11	13		T15	195
valid_sources[0x52]	104422	1			T22	1		T11	27		T15	193
valid_sources[0x53]	95231	1			T22	2		T27	4		T11	9
valid_sources[0x54]	89951	1			T22	2		T29	53		T11	12
valid_sources[0x55]	97309	1			T22	1		T11	17		T15	187
valid_sources[0x56]	95156	1			T22	4		T26	1		T29	76
valid_sources[0x57]	107552	1			T25	2		T11	17		T15	208
valid_sources[0x58]	95025	1			T22	2		T26	4		T27	4
valid_sources[0x59]	93667	1			T22	3		T26	1		T29	166
valid_sources[0x5a]	91627	1			T22	1		T27	9		T11	22
valid_sources[0x5b]	99223	1			T26	1		T27	4		T11	11
valid_sources[0x5c]	90857	1			T22	1		T11	20		T15	193
valid_sources[0x5d]	98235	1			T22	1		T29	46		T11	6
valid_sources[0x5e]	89730	1			T22	1		T27	7		T11	9
valid_sources[0x5f]	107480	1			T22	1		T26	2		T11	24
valid_sources[0x60]	101569	1			T22	2		T26	1		T27	1
valid_sources[0x61]	98466	1			T22	2		T26	3		T11	5
valid_sources[0x62]	91211	1			T27	24		T11	16		T15	187
valid_sources[0x63]	97362	1			T11	27		T15	195		T17	7
valid_sources[0x64]	90832	1			T22	1		T25	1		T26	1
valid_sources[0x65]	99226	1			T26	2		T11	21		T15	182
valid_sources[0x66]	101969	1			T26	1		T11	9		T15	174
valid_sources[0x67]	91502	1			T25	1		T26	2		T27	3
valid_sources[0x68]	100298	1			T22	1		T27	1		T11	8
valid_sources[0x69]	99383	1			T22	7		T25	5		T26	2
valid_sources[0x6a]	104268	1			T22	1		T26	2		T29	47
valid_sources[0x6b]	104303	1			T22	1		T29	17		T11	16
valid_sources[0x6c]	89517	1			T22	3		T26	2		T11	20
valid_sources[0x6d]	96618	1			T22	3		T27	2		T11	32
valid_sources[0x6e]	94098	1			T27	3		T29	16		T11	31
valid_sources[0x6f]	89887	1			T22	1		T26	1		T11	9
valid_sources[0x70]	92405	1			T22	1		T25	2		T11	9
valid_sources[0x71]	96732	1			T22	3		T11	29		T15	193
valid_sources[0x72]	96366	1			T22	2		T25	6		T27	12
valid_sources[0x73]	108542	1			T26	3		T11	11		T15	207
valid_sources[0x74]	101364	1			T22	1		T24	636		T25	6
valid_sources[0x75]	93819	1			T29	9		T11	9		T15	190
valid_sources[0x76]	97588	1			T22	3		T29	138		T11	9
valid_sources[0x77]	205543	1			T22	6		T27	3		T11	40
valid_sources[0x78]	97203	1			T22	4		T11	10		T15	204
valid_sources[0x79]	98679	1			T22	5		T23	1542		T29	85
valid_sources[0x7a]	103582	1			T22	1		T11	26		T15	212
valid_sources[0x7b]	89866	1			T22	1		T26	1		T27	1
valid_sources[0x7c]	159454	1			T22	2		T25	3		T27	2
valid_sources[0x7d]	95435	1			T22	1		T25	4		T26	1
valid_sources[0x7e]	90847	1			T22	2		T26	2		T11	15
valid_sources[0x7f]	99124	1			T22	3		T11	21		T15	193
valid_sources[0x80]	103307	1			T11	18		T14	11		T15	193

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5870149

1

T22

65

T23

621

T24

141

values[0x0]

all_enables

biggest_size

7544367

1

T22

146

T23

186

T24

185

values[0x1]

all_enables

biggest_size

7540900

1

T22

142

T23

186

T24

180