Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	202029789	0	0	0
ctrl_en_input_filter_rd_A	202029789	43497	0	0
intr_ctrl_en_falling_rd_A	202029789	43666	0	0
intr_ctrl_en_lvlhigh_rd_A	202029789	43479	0	0
intr_ctrl_en_lvllow_rd_A	202029789	44364	0	0
intr_ctrl_en_rising_rd_A	202029789	43083	0	0
intr_enable_rd_A	202029789	43958	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202029789	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202029789	43497	0	0
T1	115538	3308	0	0
T2	0	136	0	0
T3	0	327	0	0
T4	0	320	0	0
T5	0	2601	0	0
T6	0	2967	0	0
T7	0	354	0	0
T8	0	102	0	0
T9	0	335	0	0
T10	0	314	0	0
T11	10722	0	0	0
T12	29019	0	0	0
T13	9423	0	0	0
T14	4819	0	0	0
T15	238044	0	0	0
T16	1829	0	0	0
T17	14409	0	0	0
T18	4930	0	0	0
T19	119563	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202029789	43666	0	0
T1	115538	3767	0	0
T2	0	134	0	0
T3	0	255	0	0
T4	0	313	0	0
T5	0	2952	0	0
T6	0	3425	0	0
T7	0	370	0	0
T8	0	83	0	0
T11	10722	0	0	0
T12	29019	0	0	0
T13	9423	0	0	0
T14	4819	0	0	0
T15	238044	0	0	0
T16	1829	0	0	0
T17	14409	0	0	0
T18	4930	0	0	0
T19	119563	0	0	0
T20	0	7	0	0
T21	0	3	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202029789	43479	0	0
T1	115538	3379	0	0
T2	0	104	0	0
T3	0	270	0	0
T4	0	304	0	0
T5	0	3076	0	0
T6	0	2766	0	0
T7	0	333	0	0
T8	0	50	0	0
T9	0	291	0	0
T10	0	274	0	0
T11	10722	0	0	0
T12	29019	0	0	0
T13	9423	0	0	0
T14	4819	0	0	0
T15	238044	0	0	0
T16	1829	0	0	0
T17	14409	0	0	0
T18	4930	0	0	0
T19	119563	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202029789	44364	0	0
T1	115538	3050	0	0
T2	0	108	0	0
T3	0	440	0	0
T4	0	332	0	0
T5	0	3163	0	0
T6	0	3330	0	0
T7	0	344	0	0
T8	0	139	0	0
T9	0	306	0	0
T11	10722	0	0	0
T12	29019	0	0	0
T13	9423	0	0	0
T14	4819	0	0	0
T15	238044	0	0	0
T16	1829	0	0	0
T17	14409	0	0	0
T18	4930	0	0	0
T19	119563	0	0	0
T21	0	9	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202029789	43083	0	0
T1	115538	3468	0	0
T2	0	121	0	0
T3	0	334	0	0
T4	0	330	0	0
T5	0	2873	0	0
T6	0	3059	0	0
T7	0	313	0	0
T8	0	103	0	0
T9	0	304	0	0
T10	0	368	0	0
T11	10722	0	0	0
T12	29019	0	0	0
T13	9423	0	0	0
T14	4819	0	0	0
T15	238044	0	0	0
T16	1829	0	0	0
T17	14409	0	0	0
T18	4930	0	0	0
T19	119563	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202029789	43958	0	0
T1	115538	3373	0	0
T2	0	96	0	0
T3	0	332	0	0
T4	0	334	0	0
T5	0	2975	0	0
T6	0	3147	0	0
T7	0	296	0	0
T8	0	92	0	0
T9	0	303	0	0
T11	10722	0	0	0
T12	29019	0	0	0
T13	9423	0	0	0
T14	4819	0	0	0
T15	238044	0	0	0
T16	1829	0	0	0
T17	14409	0	0	0
T18	4930	0	0	0
T19	119563	0	0	0
T21	0	10	0	0