Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3536312	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15474426

1

T21

314

T22

254

T23

104

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7672787	1			T21	83		T22	31		T23	40
values[0x0]	5578969	1			T21	127		T22	113		T23	41
values[0x1]	5758982	1			T21	147		T22	127		T23	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2727332	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16283406

1

T21

321

T22

257

T23

107

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	67331	1			T21	1		T28	902		T30	7
valid_sources[0x01]	74862	1			T24	3		T28	810		T30	4
valid_sources[0x02]	74387	1			T21	6		T22	2		T28	882
valid_sources[0x03]	69360	1			T21	3		T27	2		T28	938
valid_sources[0x04]	70068	1			T21	2		T22	2		T27	5
valid_sources[0x05]	69635	1			T21	1		T28	891		T30	2
valid_sources[0x06]	69244	1			T27	2		T28	908		T30	8
valid_sources[0x07]	69347	1			T21	2		T22	2		T28	821
valid_sources[0x08]	210539	1			T22	1		T27	4		T28	951
valid_sources[0x09]	70790	1			T28	924		T67	1		T68	2
valid_sources[0x0a]	65526	1			T21	2		T22	2		T28	910
valid_sources[0x0b]	68045	1			T22	3		T25	7		T28	937
valid_sources[0x0c]	70992	1			T21	6		T22	1		T28	916
valid_sources[0x0d]	82194	1			T22	3		T28	1010		T30	5
valid_sources[0x0e]	75064	1			T21	1		T28	766		T30	3
valid_sources[0x0f]	66206	1			T22	5		T28	1072		T30	1
valid_sources[0x10]	66972	1			T21	1		T22	1		T28	1024
valid_sources[0x11]	71664	1			T21	2		T24	1		T27	1
valid_sources[0x12]	71689	1			T21	1		T27	1		T28	1054
valid_sources[0x13]	83209	1			T21	1		T28	817		T30	8
valid_sources[0x14]	67757	1			T21	3		T22	1		T28	831
valid_sources[0x15]	67963	1			T21	3		T27	16		T28	951
valid_sources[0x16]	67299	1			T27	13		T28	879		T30	8
valid_sources[0x17]	77104	1			T21	9		T22	3		T27	5
valid_sources[0x18]	75577	1			T21	3		T22	3		T28	817
valid_sources[0x19]	70981	1			T21	4		T22	2		T28	948
valid_sources[0x1a]	68535	1			T22	1		T24	2		T28	886
valid_sources[0x1b]	71327	1			T21	5		T28	810		T30	4
valid_sources[0x1c]	70604	1			T21	1		T22	1		T27	1
valid_sources[0x1d]	74239	1			T21	3		T22	2		T24	1
valid_sources[0x1e]	72369	1			T21	2		T27	9		T28	804
valid_sources[0x1f]	68979	1			T21	4		T28	834		T30	5
valid_sources[0x20]	67968	1			T25	5		T28	988		T30	5
valid_sources[0x21]	68135	1			T22	1		T27	2		T28	964
valid_sources[0x22]	69874	1			T21	2		T22	1		T28	807
valid_sources[0x23]	70528	1			T22	2		T27	1		T28	885
valid_sources[0x24]	72300	1			T22	1		T27	1		T28	796
valid_sources[0x25]	76997	1			T27	2		T28	950		T30	6
valid_sources[0x26]	191577	1			T21	1		T22	1		T27	6
valid_sources[0x27]	65437	1			T22	1		T28	903		T30	3
valid_sources[0x28]	132941	1			T21	7		T27	1		T28	974
valid_sources[0x29]	69819	1			T22	2		T28	929		T30	8
valid_sources[0x2a]	66710	1			T21	4		T24	1		T27	3
valid_sources[0x2b]	73949	1			T21	1		T22	5		T28	887
valid_sources[0x2c]	69614	1			T22	12		T28	862		T30	4
valid_sources[0x2d]	69145	1			T21	1		T28	827		T30	9
valid_sources[0x2e]	89097	1			T21	1		T27	14		T28	921
valid_sources[0x2f]	73334	1			T22	1		T28	801		T30	5
valid_sources[0x30]	70441	1			T28	850		T30	3		T59	2
valid_sources[0x31]	71791	1			T28	922		T30	7		T59	2
valid_sources[0x32]	67612	1			T21	4		T27	1		T28	904
valid_sources[0x33]	69156	1			T21	1		T22	2		T28	910
valid_sources[0x34]	66848	1			T22	2		T27	15		T28	954
valid_sources[0x35]	67767	1			T21	4		T24	3		T28	986
valid_sources[0x36]	70126	1			T21	3		T28	839		T30	16
valid_sources[0x37]	70868	1			T22	2		T28	959		T30	3
valid_sources[0x38]	69505	1			T27	6		T28	876		T30	14
valid_sources[0x39]	66005	1			T28	900		T30	2		T59	3
valid_sources[0x3a]	67221	1			T21	5		T28	1010		T30	4
valid_sources[0x3b]	68355	1			T21	1		T28	976		T59	1
valid_sources[0x3c]	74035	1			T21	4		T22	2		T27	21
valid_sources[0x3d]	70270	1			T21	7		T22	1		T28	980
valid_sources[0x3e]	72067	1			T21	1		T27	1		T28	948
valid_sources[0x3f]	69158	1			T21	4		T22	1		T25	4
valid_sources[0x40]	66213	1			T21	1		T25	10		T28	911
valid_sources[0x41]	66299	1			T21	1		T22	4		T24	2
valid_sources[0x42]	69195	1			T21	5		T22	2		T24	7
valid_sources[0x43]	65033	1			T21	2		T22	1		T27	4
valid_sources[0x44]	73550	1			T21	3		T22	2		T28	810
valid_sources[0x45]	71229	1			T28	903		T30	16		T59	2
valid_sources[0x46]	68384	1			T21	1		T22	3		T24	4
valid_sources[0x47]	70966	1			T21	2		T27	2		T28	965
valid_sources[0x48]	69013	1			T21	4		T28	895		T30	6
valid_sources[0x49]	68841	1			T25	1		T27	2		T28	791
valid_sources[0x4a]	70423	1			T22	1		T28	893		T30	1
valid_sources[0x4b]	67758	1			T22	3		T27	15		T28	961
valid_sources[0x4c]	68319	1			T21	1		T22	3		T28	872
valid_sources[0x4d]	70075	1			T27	6		T28	939		T30	7
valid_sources[0x4e]	69779	1			T28	887		T30	10		T59	2
valid_sources[0x4f]	71906	1			T21	8		T27	9		T28	866
valid_sources[0x50]	77233	1			T21	2		T28	880		T30	3
valid_sources[0x51]	75444	1			T21	1		T22	3		T23	122
valid_sources[0x52]	68653	1			T21	1		T27	9		T28	907
valid_sources[0x53]	68358	1			T27	6		T28	876		T30	4
valid_sources[0x54]	69658	1			T21	1		T27	3		T28	922
valid_sources[0x55]	110965	1			T21	1		T22	1		T28	937
valid_sources[0x56]	69840	1			T21	2		T24	1		T28	904
valid_sources[0x57]	69809	1			T27	3		T28	936		T30	3
valid_sources[0x58]	69546	1			T21	2		T22	4		T28	932
valid_sources[0x59]	67878	1			T22	3		T28	828		T30	5
valid_sources[0x5a]	67466	1			T22	1		T28	886		T30	2
valid_sources[0x5b]	67056	1			T22	1		T28	854		T67	2
valid_sources[0x5c]	108431	1			T21	3		T28	999		T30	3
valid_sources[0x5d]	67035	1			T21	1		T22	1		T27	1
valid_sources[0x5e]	73412	1			T22	1		T24	1		T28	999
valid_sources[0x5f]	72775	1			T28	919		T30	4		T59	1
valid_sources[0x60]	152077	1			T22	1		T27	6		T28	936
valid_sources[0x61]	74154	1			T28	894		T30	10		T59	3
valid_sources[0x62]	80686	1			T21	1		T27	4		T28	890
valid_sources[0x63]	70831	1			T21	1		T22	7		T28	933
valid_sources[0x64]	72463	1			T21	1		T22	1		T28	999
valid_sources[0x65]	68961	1			T28	987		T30	2		T59	4
valid_sources[0x66]	68737	1			T21	2		T28	840		T30	2
valid_sources[0x67]	70365	1			T22	2		T28	994		T30	3
valid_sources[0x68]	72631	1			T27	2		T28	949		T30	12
valid_sources[0x69]	71258	1			T27	6		T28	984		T30	5
valid_sources[0x6a]	69398	1			T22	1		T28	806		T30	3
valid_sources[0x6b]	70403	1			T21	1		T22	3		T24	1
valid_sources[0x6c]	73357	1			T21	1		T22	2		T27	15
valid_sources[0x6d]	68746	1			T22	2		T28	858		T30	2
valid_sources[0x6e]	67113	1			T28	921		T30	10		T59	1
valid_sources[0x6f]	71229	1			T21	1		T22	3		T27	7
valid_sources[0x70]	69227	1			T21	1		T22	2		T28	851
valid_sources[0x71]	79309	1			T21	6		T22	3		T27	8
valid_sources[0x72]	68272	1			T21	2		T28	1078		T30	5
valid_sources[0x73]	72563	1			T21	1		T27	1		T28	968
valid_sources[0x74]	73579	1			T21	1		T27	2		T28	897
valid_sources[0x75]	65620	1			T21	2		T22	1		T28	789
valid_sources[0x76]	70326	1			T24	1		T27	1		T28	857
valid_sources[0x77]	72500	1			T21	1		T28	969		T30	6
valid_sources[0x78]	67410	1			T21	2		T28	893		T30	4
valid_sources[0x79]	69892	1			T28	910		T30	7		T59	7
valid_sources[0x7a]	68108	1			T22	2		T27	3		T28	847
valid_sources[0x7b]	72073	1			T21	1		T22	2		T28	875
valid_sources[0x7c]	68954	1			T21	3		T28	923		T30	7
valid_sources[0x7d]	70850	1			T24	1		T28	908		T30	7
valid_sources[0x7e]	68941	1			T22	1		T24	1		T28	895
valid_sources[0x7f]	71704	1			T21	1		T22	2		T27	7
valid_sources[0x80]	71344	1			T21	2		T24	2		T27	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4353974

1

T21

40

T22

14

T23

22

values[0x0]

all_enables

biggest_size

5560891

1

T21

127

T22

113

T23

41

values[0x1]

all_enables

biggest_size

5559561

1

T21

147

T22

127

T23

41