Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	149168873	0	0	0
ctrl_en_input_filter_rd_A	149168873	65692	0	0
intr_ctrl_en_falling_rd_A	149168873	65695	0	0
intr_ctrl_en_lvlhigh_rd_A	149168873	64893	0	0
intr_ctrl_en_lvllow_rd_A	149168873	67215	0	0
intr_ctrl_en_rising_rd_A	149168873	64979	0	0
intr_enable_rd_A	149168873	64921	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149168873	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149168873	65692	0	0
T1	15467	110	0	0
T2	47933	220	0	0
T3	0	1201	0	0
T4	0	2752	0	0
T5	0	3	0	0
T6	0	302	0	0
T7	0	255	0	0
T8	0	60	0	0
T9	0	27638	0	0
T10	0	2	0	0
T11	34868	0	0	0
T12	1745	0	0	0
T13	9104	0	0	0
T14	2333	0	0	0
T15	24927	0	0	0
T16	3800	0	0	0
T17	49701	0	0	0
T18	2562	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149168873	65695	0	0
T1	15467	107	0	0
T2	47933	209	0	0
T3	0	1170	0	0
T4	0	2745	0	0
T6	0	240	0	0
T7	0	267	0	0
T8	0	127	0	0
T9	0	28781	0	0
T10	0	9	0	0
T11	34868	0	0	0
T12	1745	0	0	0
T13	9104	0	0	0
T14	2333	0	0	0
T15	24927	0	0	0
T16	3800	0	0	0
T17	49701	0	0	0
T18	2562	0	0	0
T19	0	113	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149168873	64893	0	0
T1	15467	133	0	0
T2	47933	169	0	0
T3	0	1163	0	0
T4	0	2784	0	0
T5	0	1	0	0
T6	0	265	0	0
T7	0	370	0	0
T8	0	53	0	0
T9	0	27173	0	0
T11	34868	0	0	0
T12	1745	0	0	0
T13	9104	0	0	0
T14	2333	0	0	0
T15	24927	0	0	0
T16	3800	0	0	0
T17	49701	0	0	0
T18	2562	0	0	0
T19	0	121	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149168873	67215	0	0
T1	15467	127	0	0
T2	47933	294	0	0
T3	0	1318	0	0
T4	0	2793	0	0
T5	0	6	0	0
T6	0	349	0	0
T7	0	277	0	0
T8	0	87	0	0
T9	0	29345	0	0
T11	34868	0	0	0
T12	1745	0	0	0
T13	9104	0	0	0
T14	2333	0	0	0
T15	24927	0	0	0
T16	3800	0	0	0
T17	49701	0	0	0
T18	2562	0	0	0
T20	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149168873	64979	0	0
T1	15467	75	0	0
T2	47933	275	0	0
T3	0	1180	0	0
T4	0	2740	0	0
T5	0	4	0	0
T6	0	215	0	0
T7	0	291	0	0
T8	0	77	0	0
T9	0	27438	0	0
T11	34868	0	0	0
T12	1745	0	0	0
T13	9104	0	0	0
T14	2333	0	0	0
T15	24927	0	0	0
T16	3800	0	0	0
T17	49701	0	0	0
T18	2562	0	0	0
T20	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149168873	64921	0	0
T1	15467	116	0	0
T2	47933	170	0	0
T3	0	1041	0	0
T4	0	2850	0	0
T5	0	2	0	0
T6	0	210	0	0
T7	0	283	0	0
T8	0	103	0	0
T9	0	26667	0	0
T11	34868	0	0	0
T12	1745	0	0	0
T13	9104	0	0	0
T14	2333	0	0	0
T15	24927	0	0	0
T16	3800	0	0	0
T17	49701	0	0	0
T18	2562	0	0	0
T19	0	81	0	0