Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3233730 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 13902027 1 T21 42 T22 103 T23 113407



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 6960762 1 T21 13 T22 20 T23 63840
values[0x0] 5012081 1 T21 16 T22 44 T23 40730
values[0x1] 5162914 1 T21 17 T22 50 T23 40736



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2501128 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 14634629 1 T21 43 T22 104 T23 119720



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 60981 1 T23 439 T24 2 T29 1
valid_sources[0x01] 55363 1 T23 623 T24 1 T25 1
valid_sources[0x02] 59641 1 T23 458 T24 1 T25 3
valid_sources[0x03] 60678 1 T23 670 T29 3 T30 3
valid_sources[0x04] 56274 1 T23 566 T25 1 T29 2
valid_sources[0x05] 55334 1 T23 571 T24 1 T25 5
valid_sources[0x06] 65278 1 T23 654 T29 2 T30 1
valid_sources[0x07] 66134 1 T23 611 T29 4 T1 363
valid_sources[0x08] 62034 1 T23 556 T25 3 T29 6
valid_sources[0x09] 62055 1 T23 541 T25 1 T29 2
valid_sources[0x0a] 62169 1 T23 627 T25 1 T29 5
valid_sources[0x0b] 65635 1 T23 541 T25 5 T29 2
valid_sources[0x0c] 59872 1 T23 454 T24 1 T25 6
valid_sources[0x0d] 184288 1 T23 600 T24 1 T29 7
valid_sources[0x0e] 69079 1 T23 578 T25 2 T29 4
valid_sources[0x0f] 91067 1 T23 586 T24 1 T25 4
valid_sources[0x10] 60802 1 T21 2 T23 582 T25 2
valid_sources[0x11] 179857 1 T21 4 T23 581 T24 1
valid_sources[0x12] 68819 1 T23 593 T24 1 T29 1
valid_sources[0x13] 55604 1 T23 601 T24 1 T29 2
valid_sources[0x14] 56536 1 T23 492 T25 3 T29 4
valid_sources[0x15] 68449 1 T23 602 T24 2 T25 1
valid_sources[0x16] 57052 1 T23 554 T24 2 T25 3
valid_sources[0x17] 62995 1 T22 114 T23 499 T25 1
valid_sources[0x18] 69262 1 T23 525 T29 2 T30 1
valid_sources[0x19] 62722 1 T21 1 T23 622 T29 5
valid_sources[0x1a] 60701 1 T23 531 T24 1 T29 3
valid_sources[0x1b] 61910 1 T23 517 T25 3 T29 3
valid_sources[0x1c] 99118 1 T23 621 T29 3 T30 1
valid_sources[0x1d] 59395 1 T23 586 T29 3 T30 1
valid_sources[0x1e] 62600 1 T23 564 T24 1 T25 1
valid_sources[0x1f] 63426 1 T23 610 T29 2 T1 370
valid_sources[0x20] 62664 1 T23 642 T25 1 T29 2
valid_sources[0x21] 62746 1 T23 582 T25 2 T29 8
valid_sources[0x22] 59234 1 T23 557 T29 4 T30 3
valid_sources[0x23] 61075 1 T23 623 T25 3 T29 2
valid_sources[0x24] 62248 1 T23 547 T25 1 T29 5
valid_sources[0x25] 68411 1 T23 582 T25 5 T29 7
valid_sources[0x26] 55222 1 T23 588 T25 2 T29 5
valid_sources[0x27] 62609 1 T23 590 T24 3 T25 2
valid_sources[0x28] 62979 1 T23 576 T29 4 T30 3
valid_sources[0x29] 57051 1 T23 669 T25 4 T29 2
valid_sources[0x2a] 54773 1 T23 602 T25 3 T29 7
valid_sources[0x2b] 63152 1 T23 622 T24 1 T25 2
valid_sources[0x2c] 58223 1 T23 555 T25 3 T29 8
valid_sources[0x2d] 68757 1 T23 499 T25 1 T29 2
valid_sources[0x2e] 67339 1 T23 585 T24 2 T25 1
valid_sources[0x2f] 63562 1 T23 614 T25 1 T29 8
valid_sources[0x30] 59184 1 T23 457 T25 1 T29 2
valid_sources[0x31] 56380 1 T23 627 T25 2 T29 4
valid_sources[0x32] 62829 1 T23 659 T25 1 T29 3
valid_sources[0x33] 62674 1 T23 612 T25 1 T29 3
valid_sources[0x34] 65877 1 T23 576 T25 4 T29 7
valid_sources[0x35] 70350 1 T23 512 T25 1 T29 5
valid_sources[0x36] 57536 1 T23 587 T24 1 T25 4
valid_sources[0x37] 56065 1 T23 530 T25 1 T29 3
valid_sources[0x38] 55001 1 T23 563 T25 1 T29 5
valid_sources[0x39] 58589 1 T23 654 T24 1 T25 1
valid_sources[0x3a] 66648 1 T23 588 T25 2 T29 4
valid_sources[0x3b] 80062 1 T23 505 T25 1 T29 4
valid_sources[0x3c] 63780 1 T21 1 T23 634 T24 1
valid_sources[0x3d] 59756 1 T23 623 T25 1 T30 1
valid_sources[0x3e] 60874 1 T23 581 T25 1 T29 2
valid_sources[0x3f] 58273 1 T21 1 T23 603 T25 2
valid_sources[0x40] 60184 1 T23 583 T25 1 T29 4
valid_sources[0x41] 72446 1 T23 526 T25 3 T29 2
valid_sources[0x42] 59829 1 T23 595 T25 1 T29 1
valid_sources[0x43] 89235 1 T23 552 T25 1 T29 4
valid_sources[0x44] 61515 1 T23 590 T25 2 T29 3
valid_sources[0x45] 102678 1 T23 699 T25 1 T29 6
valid_sources[0x46] 58841 1 T23 519 T24 1 T25 5
valid_sources[0x47] 60388 1 T23 576 T24 1 T25 1
valid_sources[0x48] 54938 1 T23 583 T24 1 T29 5
valid_sources[0x49] 63296 1 T23 626 T25 2 T29 2
valid_sources[0x4a] 59232 1 T23 597 T29 3 T30 2
valid_sources[0x4b] 71378 1 T23 505 T25 6 T29 1
valid_sources[0x4c] 59618 1 T23 638 T25 4 T29 6
valid_sources[0x4d] 62843 1 T23 556 T29 3 T1 412
valid_sources[0x4e] 59550 1 T23 566 T25 5 T29 6
valid_sources[0x4f] 61864 1 T23 588 T24 1 T25 1
valid_sources[0x50] 64862 1 T23 535 T25 1 T29 3
valid_sources[0x51] 63836 1 T23 564 T24 1 T25 2
valid_sources[0x52] 61210 1 T23 539 T29 5 T1 393
valid_sources[0x53] 69133 1 T23 605 T24 2 T29 3
valid_sources[0x54] 56581 1 T23 505 T25 2 T29 1
valid_sources[0x55] 61537 1 T23 628 T25 4 T29 6
valid_sources[0x56] 62532 1 T23 481 T29 4 T30 1
valid_sources[0x57] 64177 1 T23 583 T24 2 T25 1
valid_sources[0x58] 58756 1 T23 507 T25 1 T29 2
valid_sources[0x59] 58618 1 T23 434 T25 3 T29 6
valid_sources[0x5a] 62964 1 T23 538 T29 3 T1 381
valid_sources[0x5b] 65631 1 T23 485 T29 5 T1 358
valid_sources[0x5c] 63009 1 T23 535 T25 1 T29 3
valid_sources[0x5d] 226442 1 T23 556 T25 2 T29 2
valid_sources[0x5e] 58696 1 T23 502 T24 2 T30 2
valid_sources[0x5f] 65355 1 T23 537 T24 1 T25 1
valid_sources[0x60] 64993 1 T23 605 T24 2 T29 5
valid_sources[0x61] 59303 1 T23 558 T25 1 T28 143
valid_sources[0x62] 131745 1 T21 2 T23 549 T25 1
valid_sources[0x63] 60847 1 T23 551 T25 1 T29 4
valid_sources[0x64] 64090 1 T23 636 T25 3 T29 4
valid_sources[0x65] 73627 1 T23 497 T25 3 T30 5
valid_sources[0x66] 66761 1 T23 578 T25 2 T29 5
valid_sources[0x67] 62090 1 T21 1 T23 551 T24 3
valid_sources[0x68] 60980 1 T23 638 T29 4 T30 1
valid_sources[0x69] 59803 1 T23 694 T25 1 T29 1
valid_sources[0x6a] 61854 1 T23 490 T25 1 T29 2
valid_sources[0x6b] 64255 1 T21 14 T23 662 T29 1
valid_sources[0x6c] 61938 1 T23 606 T25 3 T29 2
valid_sources[0x6d] 59356 1 T23 599 T25 1 T29 4
valid_sources[0x6e] 60166 1 T23 663 T25 2 T29 1
valid_sources[0x6f] 60744 1 T23 626 T24 1 T29 4
valid_sources[0x70] 63008 1 T21 1 T23 592 T29 5
valid_sources[0x71] 65461 1 T23 560 T24 1 T25 3
valid_sources[0x72] 56631 1 T23 598 T25 3 T29 7
valid_sources[0x73] 62367 1 T23 617 T25 2 T29 5
valid_sources[0x74] 67034 1 T23 493 T25 4 T29 2
valid_sources[0x75] 60863 1 T23 563 T25 3 T29 3
valid_sources[0x76] 63774 1 T23 579 T25 2 T29 6
valid_sources[0x77] 72448 1 T21 1 T23 577 T25 1
valid_sources[0x78] 62476 1 T23 595 T25 4 T29 3
valid_sources[0x79] 64177 1 T23 606 T25 1 T29 2
valid_sources[0x7a] 64308 1 T23 596 T24 1 T25 3
valid_sources[0x7b] 65123 1 T23 542 T25 4 T29 2
valid_sources[0x7c] 57236 1 T23 609 T25 3 T29 4
valid_sources[0x7d] 61824 1 T23 518 T25 1 T29 4
valid_sources[0x7e] 62234 1 T23 654 T29 3 T30 1
valid_sources[0x7f] 69148 1 T23 519 T25 2 T29 4
valid_sources[0x80] 64191 1 T21 4 T23 562 T25 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 3913094 1 T21 9 T22 9 T23 31941
values[0x0] all_enables biggest_size 4996304 1 T21 16 T22 44 T23 40730
values[0x1] all_enables biggest_size 4992629 1 T21 17 T22 50 T23 40736

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%