Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	132407525	0	0	0
ctrl_en_input_filter_rd_A	132407525	59609	0	0
intr_ctrl_en_falling_rd_A	132407525	60296	0	0
intr_ctrl_en_lvlhigh_rd_A	132407525	60380	0	0
intr_ctrl_en_lvllow_rd_A	132407525	61188	0	0
intr_ctrl_en_rising_rd_A	132407525	59972	0	0
intr_enable_rd_A	132407525	60005	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132407525	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132407525	59609	0	0
T1	127006	4666	0	0
T2	0	142	0	0
T3	0	245	0	0
T4	0	2996	0	0
T5	0	394	0	0
T6	0	3071	0	0
T7	0	2039	0	0
T8	0	62	0	0
T9	0	1899	0	0
T10	0	157	0	0
T11	5603	0	0	0
T12	5333	0	0	0
T13	2889	0	0	0
T14	2737	0	0	0
T15	5633	0	0	0
T16	8414	0	0	0
T17	8463	0	0	0
T18	4521	0	0	0
T19	5930	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132407525	60296	0	0
T1	127006	4733	0	0
T2	0	176	0	0
T3	0	290	0	0
T4	0	2948	0	0
T5	0	356	0	0
T6	0	2964	0	0
T7	0	2143	0	0
T8	0	110	0	0
T9	0	2005	0	0
T11	5603	0	0	0
T12	5333	0	0	0
T13	2889	0	0	0
T14	2737	0	0	0
T15	5633	0	0	0
T16	8414	0	0	0
T17	8463	0	0	0
T18	4521	0	0	0
T19	5930	0	0	0
T20	0	2	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132407525	60380	0	0
T1	127006	4781	0	0
T2	0	166	0	0
T3	0	255	0	0
T4	0	2760	0	0
T5	0	324	0	0
T6	0	3044	0	0
T7	0	2032	0	0
T8	0	92	0	0
T9	0	1809	0	0
T10	0	181	0	0
T11	5603	0	0	0
T12	5333	0	0	0
T13	2889	0	0	0
T14	2737	0	0	0
T15	5633	0	0	0
T16	8414	0	0	0
T17	8463	0	0	0
T18	4521	0	0	0
T19	5930	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132407525	61188	0	0
T1	127006	4810	0	0
T2	0	155	0	0
T3	0	160	0	0
T4	0	3094	0	0
T5	0	377	0	0
T6	0	3065	0	0
T7	0	2021	0	0
T8	0	91	0	0
T9	0	2142	0	0
T10	0	153	0	0
T11	5603	0	0	0
T12	5333	0	0	0
T13	2889	0	0	0
T14	2737	0	0	0
T15	5633	0	0	0
T16	8414	0	0	0
T17	8463	0	0	0
T18	4521	0	0	0
T19	5930	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132407525	59972	0	0
T1	127006	4775	0	0
T2	0	166	0	0
T3	0	238	0	0
T4	0	2936	0	0
T5	0	381	0	0
T6	0	3112	0	0
T7	0	1851	0	0
T8	0	82	0	0
T9	0	1872	0	0
T11	5603	0	0	0
T12	5333	0	0	0
T13	2889	0	0	0
T14	2737	0	0	0
T15	5633	0	0	0
T16	8414	0	0	0
T17	8463	0	0	0
T18	4521	0	0	0
T19	5930	0	0	0
T20	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132407525	60005	0	0
T1	127006	4623	0	0
T2	0	144	0	0
T3	0	214	0	0
T4	0	2732	0	0
T5	0	397	0	0
T6	0	3039	0	0
T7	0	1911	0	0
T8	0	88	0	0
T9	0	2106	0	0
T10	0	135	0	0
T11	5603	0	0	0
T12	5333	0	0	0
T13	2889	0	0	0
T14	2737	0	0	0
T15	5633	0	0	0
T16	8414	0	0	0
T17	8463	0	0	0
T18	4521	0	0	0
T19	5930	0	0	0